SOC infrastructure Development Lead

Job Description

SoC Infrastructure Development Lead

Experience: 8+ years in SoC architecture, infrastructure IPs, and system-level integration

Role Overview

We are looking for a highly experienced and technically strong SoC Infrastructure Development Lead to drive design, integration, and verification of infrastructure IPs that form the backbone of our complex SoC platforms. This role requires deep domain knowledge of infrastructure components such as interconnects, clocks, resets, power domains, debug fabric, and system control blocks, and the ability to coordinate across silicon, firmware, verification, and physical design teams.

Key Responsibilities

SoC Infrastructure Planning and Development

- Define and drive infrastructure architecture for complex SoCs including clocking, resets, power management, interconnects (e.g., NoC, AXI), system controllers, debug & trace, and eFuse/Fuse ROM.
- Own the design and development of key infrastructure RTL blocks such as:
- Global interrupt controllers (GIC),
- System management units (SMU),
- QoS managers,
- Low-power domain controllers (e.g., AOSS, RPMh),
- Security fuses and OTP handling blocks.

Cross-IP Integration & SoC-Level Ownership

- Drive integration and connectivity of infrastructure IPs with CPU, GPU, memory controller, peripherals, and other functional blocks via NoC or AXI fabrics.
- Define power domain partitions, reset trees, and clock domain crossings (CDC) at the SoC level.
- Work with physical design (PD) and architecture teams to optimize floorplan, area, and timing closure for infrastructure-heavy SoCs.

Design Enablement & Firmware Interface

- Collaborate with firmware and bootloader teams to define software-visible control registers (CSR), MMIO maps, and secure/non-secure access policies.
- Provide clear hardware/software interface (HSI) documentation and support integration of infrastructure blocks into platform bring-up (e.g., LK, UEFI, ATF).
- Define abstraction layers and APIs for infrastructure management in Linux/RTOS device trees or ACPI tables.

Verification and Validation

- Partner with verification teams to develop test plans, checkers, assertions, and UVM environments for all infra blocks.
- Drive pre-silicon and post-silicon validation for infrastructure IPs, and help debug corner-case bugs related to interconnects, power, or clocking.
- Participate in FPGA/emulation/system validation for early firmware bring-up.

Required Expertise

Technical Skills

- Strong RTL design skills using Verilog/SystemVerilog; familiarity with UVM and formal verification flows.
- In-depth knowledge of AMBA (AXI/AHB/APB), NoC, and coherent interconnects (e.g., CCN, CMN, or NOC from Arteris/NVIDIA).
- Expertise in clock tree design, clock gating strategies, and multi-domain reset and power sequencing.
- Experience with RTL-to-GDSII flows, including timing constraints, SDC generation, and ECO handling.

Platform-Specific Expertise

- Experience working on Qualcomm, ARM, Intel, or custom ASIC platforms, with a solid understanding of SoC assembly and platform integration.
- Familiarity with:
- Qualcomm AOSS, RPMh, and RPM message protocol,
- ARM Coresight & debug/mem-ap infrastructure,
- Secure boot, eFuse management, and system control registers,
- DVFS, retention/idle states, and power collapse flows.

Tools & Methodologies

- Proficient with tools like Synopsys Design Compiler, Primetime, VCS, SpyGlass, Questa, or Jasper.
- Working knowledge of scripts in Python/TCL/Perl for automation of flow and register map generation.
- Hands-on experience with hardware-software co-validation platforms (e.g., Synopsys ZeBu, Cadence Palladium, FPGA protos).

Soft Skills

- Strong leadership and mentoring ability across junior RTL/PD/firmware teams.
- Excellent communication for cross-functional collaboration (architecture, PD, firmware, verification, systems).
- Structured problem solving, analytical thinking, and SoC-level debug expertise.

Preferred Qualifications

- B.E./B.Tech or M.S. in Electronics, Electrical, or Computer Engineering.
- Experience leading SoC tape-outs (16nm and below nodes).
- Exposure to TSMC/Intel/Samsung process techs and PPA tradeoffs.
- Contributions to open-source SoC architecture or Linux kernel SoC drivers are a plus.

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