Urgent Principal IO Mixed Signal Design Engineer

Job Description Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B) global organization We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our we affectionately refer to it as the and it's won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you. Visit our page to see what exciting opportunities and company await Job Description: As a member of Microchip's engineering community, the mixed signal design engineer will be responsible for integration and verification of mixed signal blocks in high-speed IO's in FPGA's. The successful candidate will be involved in floor planning, place and route, timing closure and integration of mixed signal blocks in the IOs. Duties & Responsibilities - Responsible for the integration of mixed signal blocks in the IO, which includes generation of constraint files, floor planning and place and route of performance critical digital blocks in the IO signal path, and timing closure using STA. - Develop and integrate custom mixed signal circuits for high-speed DDR and other IO applications in advanced FinFET nodes. Experience in place and route, timing closure is required. - Work with the IO lead to understand the design requirements and translate them into circuit architectures, implement and simulate them. - Work closely with layout engineers on floorplan, placement and routing of their designs. Create efficient power delivery and signal routing topology to reduce congestion. - Deliver to the chip lead all collaterals such as Verilog and functional models, timing libraries, netlists for chip level integration. - Perform co-sim and AMS simulation to verify functionality of designs as and when necessary - Evaluate new design architectures and integration techniques to continuously improve the current and future IO design. - Support IO Mixed-Signal IP through post-tapeout phase, including lab testing, customer bring-up and debug Requirements/Qualifications: Experience Required - 10+ years of experience in place and route and timing closure of mixed signal blocks in complex SoC. - Experience with Virtuoso schematic capture tool. - Experience with Tempus, Innovus and other ASIC tools. Requirements - Minimum of 10years of successful prior IO development and verification efforts. - Experience in ASIC methodology and familiarity with ASIC tools like Innovus and Tempus. - Competency in HSPICE, co-sim, and testbench generation and simulation. - Experience with Verilog coding - Knowledge about high-speed design techniques (DDRx, PCI-e, USB) and calibrations from an architectural and circuit design standpoint. - Demonstrated competency in scripting, managing simulation queues, and data capture plus presentation using Microsoft Office tools, including Excel. - Power analysis. - Good analytical, oral and written communication skills - Able to write clean, readable presentations. - Self-motivated, proactive team player. - Ability to work to schedule requirements. Beneficial Experience - Experience with FPGA is preferred. - Experience with Memory interfaces and SerDes interfaces. - Familiarity with DFT and place and route.