Asic Rtl Design Engineer
5 days ago
Greetings from Tech Mahindra We are hiring Champions in Semicon Industry for exciting career opportunities across various roles Skill detailed are as below, please take time to go through and do please refer also your friends. Tech Mahindra Hiring ASIC RTL Engineers for Bengaluru. Exp:4-15yrs Location: Bengaluru NP: 0-30days Asic RTL Design, Lint, CDC, Spyglass JD: - The person would need the ability to elaborate RTL and read in constraints using either Genus or FC to check on syntactical sanity of constraints - Would need a good understanding of RTL clocking structures and develop an understanding of the overall subsystem (which block consumes which clocks and where the timing needs to be met vs. can be ignored) - Understanding of clock grouping concepts, constraints change across DVFS corners - Delivering of constraints at multiple levels of partitioning. Implementation constraints vs. signoff constraints. Porting of constraints from partition level to top level. - Overall understanding and delivery of the functional correctness or the constraints. - Porting over constraints from a third-party IP to constraints. Kindly share also below details. Current CTC - Expected CTC- Notice period - Holding any offer in hand - Reason for job change – Total years of experience – Relevant Years of experience - If interested share cv to ramya.k1@techmahindra.com
-
Rtl Design Verification Engineer
3 days ago
Yelahanka, India ACL Digital Full timeSOC RTL Design Verification Experience: 4 to 10 Years Location: Bangalore Key Responsibilities: - Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification - Development and verification of post-si validation sequences using C/C++ - Create methodology-based (UVM)...
-
Senior Engineer
5 days ago
Yelahanka, India Tessolve Full timeessolve – STA Engineer (4+ Years Experience) Location: Bangalore Job Type: Full-Time Experience: 4–8 years Domain: ASIC / SoC – Static Timing Analysis Job Summary Tessolve is seeking a skilled STA Engineer with 4+ years of hands-on experience in block-level and/or chip-level timing analysis and closure. The ideal candidate should be proficient with...
-
Sr. Engineer/Lead, Digital Ip/Rtl Design
3 days ago
Yelahanka, India L&T Semiconductor Technologies Full timePosition Overview: In this role, you will be responsible for design and implementation of Digital IPs for cutting-edge SoC projects. Work on implementing IP definitions that meet customer and application needs. This role requires a strong background in design methodologies, hands-on experience with industry-standard tools, and the ability to lead/participate...
-
Memory Design Engineer
7 days ago
Yelahanka, India ACL Digital Full timeJob Title: Memory Design Engineer Experience Required: 2+ Years Location: Bangalore Job Type: Full-time Industry: Semiconductors / VLSI / Memory IP Job Summary: We are seeking a skilled Memory Design Engineer to join our advanced memory IP development team. The candidate will be responsible for architecting, designing, and validating high-performance and...
-
Senior Lead Engineer – FPGA Design
3 weeks ago
Yelahanka, India Raytheon Technologies Full timeUnspecified Job Title: Principal Engineer – FPGA Design (DO-254, DAL A/B Projects) Joining our team isn’t just about finding a job; it’s about being part of a mission-critical journey to deliver world-class avionics solutions. We value innovation, technical leadership, and excellence in compliance with aerospace standards. What You Will Do: Develop...
-
Dft Engineer
5 days ago
Yelahanka, India ScaleFlux Full timeJob Title: DFT Lead Location: Bangalore, Karnataka, India. Company and Candidature Brief: At ScaleFlux, we are a family unit powered by diversity, inclusion, transparency, respect, integrity, and passion—for both our clients and our people. Our business growth depends on your professional development, as we collaborate, share ideas and innovations, and...
-
Dft Lead Engineer
5 days ago
Yelahanka, India 7Rays Semiconductors Full timeJob Description- - The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these. - The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts. - Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and...
-
Dft Engineer – Pmbist
7 days ago
Yelahanka, India Proxelera Full timeHi, If PMBIST is your playground and you enjoy owning DFT from architecture to sign-off, this role will feel like home. You’ll work on complex SoCs, shape test strategy, and solve the kind of debug challenges that actually stretch you. What you’ll handle - PMBIST Or Programmable Memory Built-In Self-Test design, integration, and verification - Test...
-
Lead Soc Verification Engineer
5 days ago
Yelahanka, India Silicon Patterns Full timeLead SoC Verification Engineer – Bengaluru 📍 Location: Bengaluru, India 🏢 Role: Lead SoC Verification Engineer 🕑 Experience: 6–12+ years About the Role We are seeking a highly skilled Lead SoC Verification Engineer to drive verification strategy and execution for cutting-edge SoC designs. This role requires deep expertise in SoC Verification...
-
Datacom Testing
3 days ago
Yelahanka, India Happiest Minds Technologies Full timeRole: Senior Engineer / Lead Engineer/ Architects Experience: 2 to 15 Years Location: Bangalore, Chennai, Hyderabad Role Summary We are looking for experienced Network Test Engineers with strong Python coding ability to join our dynamic team responsible for validating high-performance, enterprise-grade networking features. The ideal candidates will have...