3 Days Left: RTL Design Engineer

4 days ago


Hyderabad India ACL Digital Full time

Job Description Job Title: RTL Design Engineers Exp Level: 2-3 yrs Loctaion: Hyderabad Job Description: 1. Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog. 2. Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams. 3. Requires strong fundamentals in digital design, timing closure, and understanding of the ASIC flow. 4. You'll debug simulation failures, implement ECOs, and support gate-level simulations. 5. Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals. 6. Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevant experience. Share resumes to [Confidential Information]



  • Hyderabad, India ACL Digital Full time

    Job Description RTL Design Engineer Experience : 2-3 years Location : Hyderabad Knowledge in RTL Coding in Verilog or VHDL Strong understanding of Logic design, Digital design, System design aspects, FPGA flow, Design Constraints etc. Knowledge in Xilinx FPGA architecture and design flows like IPI, XDC etc. Good Knowledge in Tcl, Python scripting...


  • Bengaluru, India ACL Digital Full time

    Job Description Senior RTL(ASIC) Design Engineers Experience : 5+ years Location : Bangalore SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and...


  • India STMicroelectronics Full time

    Job Description OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115+...

  • RTL Design Engineer

    1 week ago


    Hyderabad, Telangana, India ACL Digital Full time ₹ 4,00,000 - ₹ 12,00,000 per year

    RTL Design EngineerSkill: ASIC RTL Design with LINT, CDC. Experience: 1 to 3 Years Notice Period: Immediate to 15 days Share your updated resume now.


  • Ahmedabad, India AumRaj Design Systems Pvt Ltd. Full time

    Job Description VLSI Domain RTL/FPGA Design Engineer(Fresher) Min 0 - 3 Years of Experience BE/B.Tech in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or closely related degree Ahmedabad, Bangalore Roles & Responsibilities - RTL programming (Verilog/System Verilog or VHDL). - Knowledge of complete FPGA Design Development...


  • Ahmedabad, India AumRaj Design Systems Pvt Ltd. Full time

    Job Description VLSI Domain RTL/FPGA Design Engineer(Experienced) Min 3 - 7 Years of Experience BE/B.Tech in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or closely related degree Ahmedabad, Bangalore Roles & Responsibilities - RTL programming (Verilog/System Verilog or VHDL). - Knowledge of complete FPGA Design Development...

  • RTL Design Engineer

    2 days ago


    Hyderabad, India ACL Digital Full time

    Job Title: RTL Design Engineers Exp Level: 2-3 yrsLoctaion: HyderabadJob Description:Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog .Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams.Requires strong...

  • RTL Design Engineer

    4 days ago


    Hyderabad, India ACL Digital Full time

    Job Title: RTL Design Engineers Exp Level: 2-3 yrs Loctaion: Hyderabad Job Description: 1. Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog. 2. Responsibilities include ASIC/SoC IP integration, linting, synthesis, and working closely with verification teams. 3. Requires strong fundamentals in...

  • RTL Design Engineer

    2 days ago


    Hyderabad, India ACL Digital Full time

    Job Title: RTL Design Engineers Exp Level: 2-3 yrs Loctaion: Hyderabad Job Description: Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog . Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams. Requires strong fundamentals in...

  • RTL Design Engineer

    3 days ago


    Hyderabad, India ACL Digital Full time

    Job Title: RTL Design EngineersExp Level: 2-3 yrsLoctaion: HyderabadJob Description:Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog .Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams.Requires strong fundamentals in digital...