Physical Design Static Timing Analysis Engineer, Silicon
2 weeks ago
Job Description Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 5 years of experience in silicon timing closure and chip integration. - Experience in one or more static timing tools (e.g., PrimeTime, Tempus). - Experience with STA sign-off constraint authoring for full-chip level, tape-out sign-off requirements, checklists, and associated automation. Preferred qualifications: - Bachelor's degree in Computer Science or Engineering. - Experience in extraction of design parameters, QoR metrics, and analyzing data trends. - Experience in engineering across logic and physical design, top-level implementation, Global Distribution System (GDS) tape-out. - Experience in the delivery of complex silicon utilizing state-of-the-art technology process nodes. - Knowledge of semiconductor device physics and transistor characteristics. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities - Drive the sign-off timing convergence for high-performance designs. - Set up timing constraints, define the overall Static Timing Analysis (STA) methodology. - Set up the STA infrastructure and sign-off convergence flows. - Work with block owners throughout the project for sign-off timing convergence. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
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SoC Static Timing Analysis Engineer, Silicon
2 weeks ago
Bengaluru, Karnataka, India Google Full time ₹ 20,00,000 - ₹ 25,00,000 per yearMinimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.8 years of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology growth...
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Lead Static Timing Analysis
2 weeks ago
Bengaluru, India Fiori Technology Solutions Inc Full timeJob Description Back Lead Static Timing Analysis (STA) Engineer - Bangalore, India - 10+ - Full-Time We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet...
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Lead Physical Design Engineer
2 weeks ago
Bengaluru, India Silicon Patterns Full timePhysical Design Engineer Location: Bengaluru, India Experience: 6+ years About the Role We are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust...
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Lead Physical Design Engineer
1 week ago
Bengaluru, India Silicon Patterns Full timePhysical Design Engineer Location: Bengaluru, India Experience: 6+ years About the Role We are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust...
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Lead Physical Design Engineer
1 week ago
Bengaluru, India Silicon Patterns Full timePhysical Design Engineer Location: Bengaluru, India Experience: 6+ years About the Role We are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust...
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Lead Physical Design Engineer
2 weeks ago
Bengaluru, India Silicon Patterns Full timePhysical Design EngineerLocation: Bengaluru, IndiaExperience: 6+ yearsAbout the RoleWe are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust...
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Lead Physical Design Engineer
1 week ago
Bengaluru, India Silicon Patterns Full timePhysical Design EngineerLocation: Bengaluru, IndiaExperience: 6+ yearsAbout the RoleWe are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust...
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Lead Physical Design Engineer
1 week ago
Bengaluru, India Silicon Patterns Full timePhysical Design EngineerLocation: Bengaluru, IndiaExperience: 6+ yearsAbout the RoleWe are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust...
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Lead Physical Design Engineer
1 week ago
Bengaluru, India Silicon Patterns Full timePhysical Design EngineerLocation: Bengaluru, IndiaExperience: 6+ yearsAbout the RoleWe are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust...
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Lead Physical Design Engineer
1 week ago
Bengaluru, India Silicon Patterns Full timePhysical Design EngineerLocation: Bengaluru, IndiaExperience: 6+ yearsAbout the RoleWe are seeking an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus and EMIR analysis to join our VLSI design team in Bengaluru. The ideal candidate will have hands-on experience driving the full RTL-to-GDSII flow and ensuring robust...
