RTL/Design Engineer

Job Description Experience: 3.00 + years Salary: INR 2680000-3750000 / year (based on experience) Expected Notice Period: 15 Days Shift: (GMT+05:30) Asia/Kolkata (IST) Opportunity Type: Remote Placement Type: Full Time Permanent position(Payroll and Compliance to be managed by: Architect Labs) (*Note: This is a requirement for one of Uplers client - Architect Labs) What do you need for this opportunity Must have skills required: emulation, Flexibility, tapeout, Data Analysis, Verilog/System-Verilog, RTL, synthesis, Unit Level testing, Python, typescripts, SoC integration Architect Labs is Looking for: We are an AI research and product lab for chip design. Our goal is to redefine the hardware design and verification process, methodology, and tools using our proprietary AI models and systems. In that context, we are seeking mid-level front-end hardware engineers to help build and curate high-quality RTL and verification datasets for AI training and evaluation. You'll work on reviewing, debugging, coding, labeling, and generating Verilog/SystemVerilog designs, unit-level testing, and POC design development and verification. Responsibilities - Write, review, debug+fix and annotate code, waveform, specs, and hardware documents for model training and evaluation datasets. - Design & validate modular RTL designs (FIFOs, ALUs, NoCs, etc.) using our models and tools to advance our AI-enabled IP generation efforts. - Curate, document, and label RTL bugs, coding methods, and architectural definitions. - Help in prompt-tuning, generating rules and guardrails for our RTl coding agents and models. - Collaborate with ML engineers to build evaluation datasets, internal benchmarks, and evaluate model behavior and performance on RTL code. - Log quality metrics and tabulate for functionality, syntax, style, and completeness. - Partner with architects, validation engineers for documentation of in-house design. - Develop POC designs, partnering with architects, validation, and AI engineers - Synthesize eval & POC designs, own hand-off-to-backend quality convergence. - Evaluate PPA metrics, tabulate convergence progress, and send daily reports. Requirements - Bachelor's (or more) degree; 3+ years experience in RTL design (SystemVerilog). - Experience in end-to-end design flow - design, linting, ULT and synthesis, - Familiarity with standard EDA tool flows from Synopsys, Cadence, and Siemens. - Automation(Python, etc) skills for scoping & templatizing design flows and tasks. - Familiarity with SoC integration and design principles. Prefered: - Experienced in at least one product-level tape-out. - Data analytics skills, data annotation experience. - Flexibility in work hours, sync with PST timeline when needed. - Bonus if graduated from a top university like IIT, VIT, IISC, SRM, BITS, etc. Collaboration & Time Zone - You'll work remotely from India but collaborate daily with the Palo Alto team. - Must have excellent written and spoken English communication, clear, concise, and proactive. - Expect regular standups and sprint syncs with California (typically between 811 PM IST/ 710 AM PST). - We value responsiveness, initiative, and a sense of ownership that transcends time zones. How to apply for this opportunity - Step 1: Click On Apply And Register or Login on our portal. - Step 2: Complete the Screening Form & Upload updated Resume - Step 3: Increase your chances to get shortlisted & meet the client for the Interview About Uplers: Our goal is to make hiring reliable, simple, and fast. Our role will be to help all our talents find and apply for relevant contractual onsite opportunities and progress in their career. We will support any grievances or challenges you may face during the engagement. (Note: There are many more opportunities apart from this on the portal. Depending on the assessments you clear, you can apply for them as well). So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today. We are waiting for you