ASIC Verification, Principal Engineer

Job Description Principal Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and innovative ASIC Digital Design Principal Engineer with a passion for verification and a keen eye for detail. With a strong background in architecting verification environments for complex serial protocols, you are proficient in HVL (System Verilog) and have hands-on experience with industry-standard simulators. Your extensive experience includes developing and implementing test plans, extracting verification metrics, and coding for functional coverage. You are well-versed in verification methodologies such as VMM, OVM, and UVM, and have a solid understanding of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB. Your familiarity with HDLs like Verilog and scripting languages such as Perl, TCL, and Python enhances your verification processes. You possess exceptional problem-solving skills, demonstrate high levels of initiative, and excel in written and oral communication. Your collaborative spirit enables you to work closely with RTL designers and seamlessly integrate into a global team of professional verification engineers, driving the next generation of connectivity protocols for commercial, enterprise, and automotive applications. What You'll Be Doing: - Specifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores. - Performing verification tasks for IP cores, including test planning and environment coding at both unit and system levels. - Developing and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals. - Managing regression and ensuring adherence to verification methodologies. - Collaborating closely with RTL designers and a global team of verification engineers. - Working on next-generation connectivity protocols for commercial, enterprise, and automotive applications. The Impact You Will Have: - Enhancing the reliability and performance of Synopsys IP cores through meticulous verification processes. - Contributing to the development of cutting-edge connectivity protocols. - Driving innovation in chip design and verification, supporting the creation of high-performance silicon chips. - Ensuring the delivery of high-quality IP cores to our customers. - Supporting the continuous improvement of verification methodologies and processes. - Fostering collaboration and knowledge sharing within a global team, enhancing overall team performance. What You'll Need: - BSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience. - Experience in architecting verification environments for complex serial protocols. - Proficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI. - Expertise in verification methodologies such as VMM, OVM, and UVM. - Knowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB. - Familiarity with Verilog and scripting languages such as Perl, TCL, and Python. - Experience with IP design and verification processes, including VIP development. Who You Are: - Detail-oriented with exceptional problem-solving skills. - Proactive and able to demonstrate high levels of initiative. - Excellent written and oral communication skills. - A collaborative team player who thrives in a global team environment. - Adaptable and capable of managing multiple tasks and priorities. The Team You'll Be A Part Of: You will be joining the DesignWare IP Verification R&D team at Synopsys, a dynamic group dedicated to specifying, designing, and implementing verification environments for synthesizable cores. Working closely with RTL designers, you will be part of a collaborative global team of professional verification engineers focused on developing the next generation of connectivity protocols for diverse applications. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.