▷ [3 Days Left] RTL Design Verification Engineer

Eximietas Hiring: ASIC SOC RTL Micro Architect Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: Eximietas Design is seeking an experienced and highly skilled RTL Micro Architect to join our growing team. As a key contributor, you will play a critical...

Lead Design Engineer As an RTL Design Lead , you will play a critical role in leading the RTL design and verification process for complex digital designs . You will manage a team of RTL engineers , collaborate with cross-functional teams, and ensure the successful implementation of high-performance, low-power designs. The ideal candidate should have a strong...

Job Description Skills: SOC Verifcation, ASIC Verification, Design Verification, Universal Verification Methodology (UVM), Open Verification Methodology, System Verilog, Senior RTL Verification Lead / RTL Verification Engineer Are you an experienced RTL Verification professional looking for your next challenge Look no further! Qualifications - BE/ME/MTech/MS...

Job Description Senior RTL(ASIC) Design Engineers Experience : 5+ years Location : Bangalore SILICON DESIGN ENGINEER THE ROLE: As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with architecture, IP design, Physical Design teams, and...

SOC RTL Design VerificationExperience: 4 to 10 YearsLocation: BangaloreKey Responsibilities:• Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification• Development and verification of post-si validation sequences using C/C++• Create methodology-based (UVM)...

SOC RTL Design VerificationExperience: 4 to 10 YearsLocation: BangaloreKey Responsibilities:• Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification• Development and verification of post-si validation sequences using C/C++• Create methodology-based (UVM)...

SOC RTL Design VerificationExperience: 4 to 10 YearsLocation: BangaloreKey Responsibilities:• Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification• Development and verification of post-si validation sequences using C/C++• Create methodology-based (UVM)...

SOC RTL Design VerificationExperience : 4 to 10 YearsLocation : BangaloreKey Responsibilities:• Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification• Development and verification of post-si validation sequences using C/C++• Create methodology-based (UVM)...

SOC RTL Design Verification Experience : 4 to 10 Years Location : Bangalore Key Responsibilities: - Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification - Development and verification of post-si validation sequences using C/C++ - Create methodology-based (UVM)...

RTL Design Engineer for Interface Controller IP development team.Position is based in Bangalore or Noida.The role would include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence.The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as...