Only 24h Left SOC DFT Engineer

SoC DFT EngineerJob Description:Scan insertion.SCAN DRC/Coverage debug.ATPG Pattern generation.Gate level simulations ( Zero delay/Timing Delay simulations).Worked on JTAG/P1500 protocols.Perl/Tcl scripting.Timing/Formal verification/PD flow knowledge is plus.Location: BangaloreNotice Period: ImmediateExperience: 5+ Years

Role: DFT EngineerLocation: Bangalore (work from office)Experience: 5+ yearsJob DescriptionWe are looking for an energetic, passionate and process oriented DFT Engineers who has extensive experience in planning, implementation and verification of DFT features for multiple SoC.Direct Responsibilities of the role, but not limited to, working on various...

Job DescriptionStrong working experience on DFT and usage of tools like Tetramax.SoC / Modem DFT for SmartphoneATPG Coverage analysis and improvementsAPTG/TFT pattern generation and optimizationCo-work with Smartphone SOC team to plan SoC/Modem DFT requirementsHandle pre-silicon DFT verification and post-silicon DFT debugDFT clocking and DFT timing...

Job Title DFT Design Engineer Location Bengaluru Experience Required 12 Years Employment Type Full-Time Role Overview We are seeking a DFT Design-for-Test Lead to define develop and optimize DFT methodologies for our advanced LiDAR SoCs This role will lead DFT strategy and execution ensuring high performance and automotive-grade quality in...

Job DescriptionAbout Analog DevicesAnalog Devices, Inc. (NASDAQ:) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat...

L&T Technology is hiring for Senior DFT Engineers / Lead DFT Engineer with 8-15 Years of experience.Job Location : BangaloreSkills Expertise should be : ATPG, SOC, ASIC DFT.

Role & responsibilitiesWe are seeking an experienced Senior Design for Testability (DFT) Engineer with a proven track record in implementing and optimizing DFT methodologies for complex SoCs and ASICs. The ideal candidate will have deep expertise in scan insertion, ATPG, MBIST, and JTAG along with strong knowledge of ASIC design flows and tape-out...

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We...

Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test (DFT) methodologies, implementation, and verification to build best-in-class System on a Chip (SOC) and IP for data center applications. The role offers the opportunity to apply your expertise in Design for Testability (DFT) methodologies and IP/SOC...

Role & responsibilities :We are seeking an experienced Senior Design for Testability (DFT) Engineer with a proven track record in implementing and optimizing DFT methodologies for complex SoCs and ASICs. The ideal candidate will have deep expertise in scan insertion, ATPG, MBIST, and JTAG along with strong knowledge of ASIC design flows and tape-out...