Principal Asic Design

4 weeks ago

Ahmedabad Gujarat, India Infinera Full time

Job Description: Principal Engineer (M)

Role:
In this role, you will be responsible for the verification of a large complex block or multiple blocks. You will work with a team of verificaiton engineers to deliver bug free ASIC.

What you will be doing:

- Work closely with peers in architecture, design, verification, emulation, SDK, Hardware teams and project team members
- Estimate the scope of work, evaluate the risks, and build the execution plan
- Provide high level and day-2-day technical guidance to verification team members
- Own the execution while working with project management team to provide weekly status

What we seek:

- Previous experience of managing a team (15+ years of experience)
- Proven delivery of ASIC projects using SV/UVM methodologies
- Strong verification skills - should be able to review the requirements, verification plan, test plan, micro-arch, identify scenarios and design intent and develop verification strategies which can ensure defect free ASIC
- Experience in driving improvements in verification methodologies
- Experience in effort estimation, identifying dependencies, identifying the skill sets required, identifying the risks for a project, execution plan, project execution, providing regular project status and conducting project reviews.
- Good communication, interpersonal skills.
- Ability to mentor and bring together engineers with differing but valid technical viewpoints
- Hiring, talent development for long term team building.
- Explore new verification methodologies to improve quality and reduce pain points in the project execution.

Contributions at a group level:

- Drive improvements in verification methodologies across the ASIC organization
- Contribute to improvements in system level architecture while working with cross-functional team members
- Drive improvements in emulation and validation methodologies
- Area of work:

- UVM/System Verilog based verification + Formal verification + Emulation, Tech. Explore and initiate New verification and validation methodologies.

**Requirements**:

- 15+ years of experience in verification with Sytem Verilog and UVM
- Proven expertise in developing the verification strategy, implementation and verification closure across projects
- Excellent communication skills
- Veification Experience in Ethernet and OTN transport related ASIC projects
- Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to_ race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment._

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