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Design Verification-dv
2 weeks ago
**Role: Design Verification-DV**
**Location: Bangalore**
- **Responsibilities**:
- Preparation of digital design test plan from requirements using Cadence-vManager / vPlanner
- Definition and creation of UVM-SV test environment, test plans, tests, and functional coverage
- Verification of signal processing and control algorithms using Cadence and MathWorks tools
- Analysis of test results, improving test coverage, and debug of unexpected design behavior
- Running and maintenance of regression runs
- 0p-Preparation and/or leading of verification reviews
- Modification and/or debug of Simulink models in mixed signal test environment
- Coordination of verification activities with abroad team members
- Cooperation with system engineering team on Jama requirements
Mandatory skills:
- Possess at least a BSEE (MSEE preferred)
- Should have 6-8yrsl years' experience in digital design and/or digital verification
- Must be knowledgeable in digital design fundamentals
- Knowledge of Universal Verification Methodology, SystemVerilog assertions, and Cadence verification tools is a must
- Experience with the usage of Jama requirements management, MATLAB/Simulink model, and Python programming is a strong plus
**Skills, Knowledge, and Aptitudes**
- Excellent communication, documentation, problem-solving and analytical skills are required
- Able to solve challenging problems during verification and debug
- Ability to supervise and mentor junior engineers
**Salary**: ₹1,500,000.00 - ₹3,000,000.00 per year
Schedule:
- Day shift
Ability to commute/relocate:
- Hyderabad, Hyderabad - 500081, Telangana: Reliably commute or planning to relocate before starting work (preferred)
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