Asic Digital Design Engr, Staff

6 months ago

Hyderabad Telangana, India Synopsys Full time

48261BR
- INDIA - Hyderabad

**Job Description and Requirements**

**_ASIC Digital Design Engineer, Lead Verification_**

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.- ASIC Digital Design/Verification Engineer, Senior_
- We’re looking for
- **_Senior ASIC Digital Design Engineer, Verification _**to join Synopsys Solutions Group, Digital IP Subsystems Team.
- Come and be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs.
- _Join the Synopsys Subsystems Team _
Based in our offices in Bangalore/Hyderabad, India, you will be a senior member of the Synopsys Solutions Group Subsystems team, which is developing high performance Digital Interface IP Subsystem solutions for DDR, PCIe, Ethernet, UFS, USB and other interface protocols.
- In this role,
- As a _Lead Verification Engineer_, you will be responsible for signing off on Subsystems Verification, working closely with the Design leads, Architect the test bench, author & Sign-off on the Test Plan, test environment, driving the life-cycle of the Subsystems from Verification requirements to release phases.

Requirements:

- Knowledge of one or more of protocols AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols.
- Programming skills such as System Verilog, TCL, Perl or Python.
- The ability to work independently, precisely and to drive innovation
- The ability to extract detailed requirements from high-level specification
- Good communication skills.- Verification Lead Engineer position will require you to:_
- Understand the Subsystem requirements/specification and author the Verification Plan
- Develop the SV UVM Test Environment, Own & bring up the test cases by coordinating with other Verification team members
- Drive the Verification closure of Subsystems with quality metrics.
- Closely work with Design Leads and own/drive the verification signoff.- Key Qualifications for Verification Engineers_
- :_
- Hands-on/Lead experience on Subsystem Verification.
- Verification experience and debug skills of IP cores and/or Subsystems and/or SOC RTL designs.
- Experience in developing System Verilog, UVM or similar HDL based test environments.
- Experience in developing and implementing test plans, extracting verification metrics, developing BFMs and similar verification components.
- Obsession with quality and finding bugs.
- Please get in touch with us. Looking forward to talk to you - Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability._

**Job Category**
- Engineering

**Country**
- India

**Job Subcategory**
- ASIC Digital Design

**Hire Type**
- Employee

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