Pe Logic Design

ResponsibilitiesAs a “Principal Engineer – Logic Design” in memory interface chip design team, you willDevelop micro-architecture and RTL design for digital components for DDR memory buffer and other mixed signal chip products.Along with logic/RTL design, you will be responsible for synthesis, quality checks (lint, clock domain crossing etc.) and...

Responsibilities As a “Principal Engineer – Logic Design” in memory interface chip design team, you will Develop micro-architecture and RTL design for digital components for DDR memory buffer and other mixed signal chip products. Along with logic/RTL design, you will be responsible for synthesis, quality checks (lint, clock domain crossing...

Overview: As Principal Engineer, which is a Full-Time position, you will design PCIe Gen5/6 Retimer controllers with possibility of Gen7 Retimer controllers in future. You may also integrate PCIe sub-systems. Sub-systems will have pre-dominantly PCIe compliant PHY and controller. **Responsibilities**: - Be a technical digital design lead - Own the design...

Job DescriptionProfessional & Technical Skills:- Must To Have Skills: Expertise in SAP Payment Engine (FS-PE).- Good To Have Skills: Knowledge of SAP Financial Services Network (FSN), SAP Banking Services, and SAP S/4HANA.- Strong understanding of SAP Payment Engine (FS-PE) architecture and configuration.- Experience in designing and implementing SAP Payment...

Professional & Technical Skills:- Must To Have Skills: Expertise in SAP Payment Engine (FS-PE).- Good To Have Skills: Knowledge of SAP Financial Services Network (FSN), SAP Banking Services, and SAP S/4HANA.- Strong understanding of SAP Payment Engine (FS-PE) architecture and configuration.- Experience in designing and implementing SAP Payment Engine (FS-PE)...

Logic MicroArchitect:Location: BangaloreWe are looking for someone who will lead the development of high-speed cutting-edge SerDes design. As the lead of the micro-architectural definition and design implementation, the selected candidate will drive logic chip design achieving data of 16Gbs and above.Experience:12+ Years of experience in PCIE G3/G4/G5 or...

CPU Architecture and Logic Design A Fortune 100 Organization Location: Bangalore Your Role and Responsibilities: As a Logic design lead in the Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the customers. Deep expertise in the implementation...

Logic MicroArchitect:Location: BangaloreWe are looking for someone who will lead the development of high-speed cutting-edge SerDes design. As the lead of the micro-architectural definition and design implementation, the selected candidate will drive logic chip design achieving data of 16Gbs and above.Experience:12+ Years of experience in PCIE G3/G4/G5 or...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Engineer Location: Ahmedabad Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design...

Introduction As a Hardware Developer at IBM, you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today’s market. Your Role and Responsibilities - As a Logic design lead...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Job Title:Lead Product EngineerLocation:BangaloreCadenceis a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver...

Role: Snap Logic Developer Location: Any Tech Mahindra Location Notice: Immediate to 30 Days Interested candidates please share their cv to Job Description: 3-5 years of Development experience in building Snap logic pipelines and Ultra pipelines, error handling, scheduling tasks & alerts, Fault Tolerance, and Error Percolation Strong Hands-on...

Role: Snap Logic DeveloperLocation: Any Tech Mahindra LocationNotice: Immediate to 30 DaysInterested candidates please share their cv to bp00835635@techmahindra.com Job Description: 3-5 years of Development experience in building Snap logic pipelines and Ultra pipelines, error handling, scheduling tasks & alerts, Fault Tolerance, and Error Percolation Strong...

Role: Snap Logic DeveloperLocation: Any Tech Mahindra LocationNotice: Immediate to 30 DaysInterested candidates please share their cv to bp00835635@techmahindra.com Job Description: 3-5 years of Development experience in building Snap logic pipelines and Ultra pipelines, error handling, scheduling tasks & alerts, Fault Tolerance, and Error Percolation Strong...

Logic MicroArchitect:Location: BangaloreWe are looking for someone who will lead the development of high-speed cutting-edge SerDes design. As the lead of the micro-architectural definition and design implementation, the selected candidate will drive logic chip design achieving data of 16Gbs and above. SoC Micro-Architect, you will play a key role in the...

**Enterprise Sales Account Executive**: **>>>>>>> This hire can be based in any major technology metro in Southern India** **At Sumo Logic, our Enterprise Sales Executives are **key members of our sales organization, with responsibility for driving growth of Sumo Logic's platform in a designated territory. We seek seasoned professionals with deep experience...

**Skills Required**: - Extensive experience in Web Methods integration platform, including design, development, and administration. - Proven expertise in Snap Logic or other iPaaS platforms, with a strong understanding of its capabilities and features. - Deep understanding of integration patterns, data formats, transformation techniques, and API...

Responsibilities: · Complete DFT ownership of projects including: · Test architecture definition. · Identifying and implementing RTL changes for DFT. · Performing scan insertion. · Developing timing constraints for test mode timing closure. · Scan and ATPG for different fault models. · Boundary scan, ACJTAG, IEEE 1500 implementation and verification....

Responsibilities:· Complete DFT ownership of projects including:· Test architecture definition.· Identifying and implementing RTL changes for DFT.· Performing scan insertion.· Developing timing constraints for test mode timing closure.· Scan and ATPG for different fault models.· Boundary scan, ACJTAG, IEEE 1500 implementation and verification.·...

Responsibilities:· Complete DFT ownership of projects including:· Test architecture definition.· Identifying and implementing RTL changes for DFT.· Performing scan insertion.· Developing timing constraints for test mode timing closure.· Scan and ATPG for different fault models.· Boundary scan, ACJTAG, IEEE 1500 implementation and verification.·...