PE Logic Design

Overview: **Responsibilities**: - Lead all the digital logic design activities on high-performance mixed signal chip products. - Develop micro-architecture and RTL design for digital components for DDR memory buffer and other mixed signal chip products. - Along with logic/RTL design, you will be responsible for synthesis, quality checks (lint, clock domain...

Responsibilities As a “Principal Engineer – Logic Design” in memory interface chip design team, you will Develop micro-architecture and RTL design for digital components for DDR memory buffer and other mixed signal chip products. Along with logic/RTL design, you will be responsible for synthesis, quality checks (lint, clock domain crossing...

Overview: **Responsibilities**: As a “Principal Engineer - Logic Design” in memory interface chip design team, you will - Develop micro-architecture and RTL design for digital components for DDR memory buffer and other mixed signal chip products. - Along with logic/RTL design, you will be responsible for synthesis, quality checks (lint, clock domain...

Job DescriptionProfessional & Technical Skills:- Must To Have Skills: Expertise in SAP Payment Engine (FS-PE).- Good To Have Skills: Knowledge of SAP Financial Services Network (FSN), SAP Banking Services, and SAP S/4HANA.- Strong understanding of SAP Payment Engine (FS-PE) architecture and configuration.- Experience in designing and implementing SAP Payment...

Professional & Technical Skills:- Must To Have Skills: Expertise in SAP Payment Engine (FS-PE).- Good To Have Skills: Knowledge of SAP Financial Services Network (FSN), SAP Banking Services, and SAP S/4HANA.- Strong understanding of SAP Payment Engine (FS-PE) architecture and configuration.- Experience in designing and implementing SAP Payment Engine (FS-PE)...

Professional& TechnicalSkills:Must To Have Skills: Expertise in SAP Payment Engine(FSPE).Good To Have Skills: Knowledge of SAP Financial Services Network(FSN) SAP Banking Services and SAPS/4HANA.Strong understanding of SAP Payment Engine (FSPE) architecture andconfiguration.Experience in designing and implementing SAP Payment Engine...

CPU Architecture and Logic DesignA Fortune 100 OrganizationLocation: BangaloreYour Role and Responsibilities:As a Logic design lead in the Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the customers.Deep expertise in the implementation of...

CPU Architecture and Logic Design A Fortune 100 Organization Location: Bangalore Your Role and Responsibilities: As a Logic design lead in the Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the customers. Deep expertise in the implementation...

Overview: **Responsibilities**: The major duties and responsibilities of the position are as follows. - Strong understanding of DFT concepts. - Strong hands-on experience in scan and ATPG for different fault models - Developing constraints for scan insertion and test mode timing closure. - Improving scan and fault coverage and pattern reduction techniques. -...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Engineer Location: Ahmedabad Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design...

Positions are open for full-time positions in the areas of SOC microarchitecture and logic design including on-chip interconnects, caches, high performance memory interface, system control, high-speed IO interfaces, and data parallel processing engine. We are looking for all levels of talent, from new college grads to advanced level of...

Responsibilities: · Complete DFT ownership of projects including: · Test architecture definition. · Identifying and implementing RTL changes for DFT. · Performing scan insertion. · Developing timing constraints for test mode timing closure. · Scan and ATPG for different fault models. · Boundary scan, ACJTAG, IEEE 1500 implementation and...

Logic MicroArchitect:Location: BangaloreWe are looking for someone who will lead the development of high-speed cutting-edge SerDes design. As the lead of the micro-architectural definition and design implementation, the selected candidate will drive logic chip design achieving data of 16Gbs and above. SoC Micro-Architect, you will play a key role in the...

Ventana Micro Systems is at the forefront of the two hottest trends that are revolutionizing the semiconductor industry: RISC-V and Chiplet Architecture. **Check out our CEO** talking with global tech analyst Patrick Moorhead about how Ventana combines the extensibility of RISC-V with chiplet technology to create customer-driven innovation for best-in-class...

SENIOR LOGIC DESIGN ENGINEER – CacheFortune 100 OrganizationLocation: BangaloreAs a Hardware Developer at , you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable our customers to make better decisions quicker on the most trusted hardware platform in today’s...

Sumo Logic is the pioneer in continuous intelligence, a new category of software, which enables organizations of all sizes to address the data challenges and opportunities presented by digital transformation, modern applications, and cloud computing. The Sumo Logic Continuous Intelligence Platform™ automates the collection, ingestion, and analysis of...

Job DescriptionRoles and ResponsibilitiesBuild, design, and deploy solutions, new integrations/APIs and update existing API functionalities (enhancements or bugfixes) on Azure Integration Services ( Logic Apps, APIM & Azure functions) and update existing APIs functionality (enhancement/defect fix); Unit/UAT Testing of the API integration.Works from written...

Responsibilities:· Complete DFT ownership of projects including:· Test architecture definition.· Identifying and implementing RTL changes for DFT.· Performing scan insertion.· Developing timing constraints for test mode timing closure.· Scan and ATPG for different fault models.· Boundary scan, ACJTAG, IEEE 1500 implementation and verification.·...

Responsibilities:· Complete DFT ownership of projects including:· Test architecture definition.· Identifying and implementing RTL changes for DFT.· Performing scan insertion.· Developing timing constraints for test mode timing closure.· Scan and ATPG for different fault models.· Boundary scan, ACJTAG, IEEE 1500 implementation and verification.·...

Responsibilities: · Complete DFT ownership of projects including: · Test architecture definition. · Identifying and implementing RTL changes for DFT. · Performing scan insertion. · Developing timing constraints for test mode timing closure. · Scan and ATPG for different fault models. · Boundary scan, ACJTAG, IEEE 1500 implementation and verification....