Rtl Design
3 weeks ago
Timing (Constraints/Synthesis/STA) Timing ASIC Constraint development, Synthesis/ STA. - Strong experience in Logic synthesis, STA, Lint and CDC checks, DFT, constraining, physical implementation - Hands-on experience in timing analysis - Experience in doing SoC level timing analysis Should be familiar with timing analysis for hierarchical designs - Familiarity with different types interfaces like PCIe, NVMe/, USB, DDR etc - Should be proficient with Synopsys &; Prime Time for timing analysis - Good scripting skill in Tcl and Perl - Familiarity with different physical design tools - knowledge of Synopsys tools - Knowledge about data management is a definite plus - Good team player working with geo-dispersed cross cultural and cross functional teams - Good communication and interpersonal skills required. Please let us know when we can have a quick discussion regarding Hardware resumes.
**Job Types**: Full-time, Regular / Permanent
**Salary**: ₹1,000,000.00 - ₹4,000,000.00 per year
Schedule:
- Day shift
Supplemental pay types:
- Performance bonus
- Yearly bonus
Ability to commute/relocate:
- Banglore, Karnataka: Reliably commute or planning to relocate before starting work (preferred)
**Experience**:
- total work: 5 years (preferred)
- RTL design: 5 years (preferred)
- ASIC constraint Development: 3 years (preferred)
- ASIC designing: 2 years (preferred)
- FPGA: 1 year (preferred)
- STA Lint: 1 year (preferred)
- DFT: 1 year (preferred)
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