RTL Design Engineer

2 months ago

Bengaluru, India Texas Instruments Full time

Experience Level : 1-2 Years Only


• 1-2 Years experience in SoC/IP RTL Design

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.



About the Group:


The Sitara MPU product line is a rapidly expanding business within TI, investing to address the fast-growing segment of high-performance processors in industrial & automotive markets

This product line will enable a scalable portfolio of ARM based high-end MPUs as emerging trends in AI & analytics, motor control, robotics, HMI and real-time networking are shaping the evolving requirements for applications like autonomous robots, renewable energy, factory and home automation.

The newly formed Sitara MPU team in India will focus on expanding the breadth of TI’s portfolio by scaling the execution of MPU devices in 16FF node and is looking for passionate folks who can partner to make this a reality




What will you be doing in this role?


• Integration for complex multi-core SOC designs.

• Quality checks of the implemented RTL for LINT, CDC.

• Run power estimation flows to check on overall SOC power and correlate with Silicon data.

• Work closely with IP and SoC verification teams to achieve high quality IP delivery.

• Provide support to constraint development and timing closure.

• Contribute and drive quality/cycle time improvement methodologies as a part of the development process.

• Be a team player working across functional teams responsible for development of IP/SoCs from spec to silicon.




What do we expect from you?

• Strong RTL design experience with SOC integration for microcontrollers expected.

• Design experience with high performance Bus Architectures, Memory Controllers for volatile/non-volatile memories and Analog-Mixed signal IPs is required.

• Experience with power estimation tool at RTL/post layout will be a plus.

• Experience on power management techniques and designs is a must

• Knowledge on functional safety will be preferred.

• Must have strong multi-clock domain design knowledge and expertise in Clock Domain Crossing (CDC) analysis tools.

• Experience in timing constraint development at SoC level and timing analysis is preferred.

• Experience with scripting and automation would be an added bonus.



Preferred Skills/ Experience


• 1-2 Years experience in SoC/IP RTL Design

• Experience in SoC integration and implementation.

Strong experience with Linting, CDC and power estimation tools are required.

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