Staff, Physical Design

6 months ago

Bengaluru Karnataka, India onsemi Full time

STA Lead with expertise in timing constraints handling for different fullchip IO protocol (I2C, DDR, USB etc )
- Generating ECO for timing closure for complex multi power domain designs
- Good experience in running STA regression with high number of modes/corners efficiently.
- Power recovery with STA signoff
- Debug constraint issues in P&R environment
- LEC/Low power checks experience
- Strong in problem solving with deep understanding of technical issues.
- Solid understanding of Verilog, TCL and Perl/Python/XML programming languages

**onsemi **(Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

More details about our company benefits can be found here:
- BS in Electrical Engineering or related + 6 years of experience, or MS + 5 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
- Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF
- Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
- Solid track record of releasing complex ICs to market
- Ability to clearly articulate issues, challenges, and concerns to all levels of management
- Must have good written and verbal cross-functional communication skills
- BS in Electrical Engineering or related + 6 years of experience, or MS + 5 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
- Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF
- Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
- Solid track record of releasing complex ICs to market
- Ability to clearly articulate issues, challenges, and concerns to all levels of management
- Must have good written and verbal cross-functional communication skills

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