Technical Staff Engineer
2 months ago
Execute standard Physical Design implementation practices.Conduct die size estimations and manage bond-out approvals.Achieve timing closure to optimize process node performance.Setup, debug, and synthesize clock trees for high-quality QoR.Design and support multi-voltage island-based floorplans.Develop and automate design flows.Deliver Physical Verification (PV)-compliant designs.Collaborate with external vendors and IP providers to resolve issues.Work closely with international design and implementation teams.
Qualifications:
Minimum
B.Tech/M.Tech
in Electronics or related field.10+ years of experience in Physical design and timing aspects of IC design, with leadership capability.Key Skills:
Expertise in VLSI logic design, clock tree synthesis/debugging, and timing closure.Proficiency in place-and-route and low-power design methodologies.Experience in system-level floorplanning, power network planning, and power integrity/reliability (EM/IR) analysis.Strong knowledge of Innovus, Redhawk, and Calibre tools.Proficiency in Tcl and Perl scripting.Excellent debugging, analytical, and leadership skills.Strong communication skills and interpersonal abilities.
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