Design Verification Engineer

1 month ago


Hyderabad Secunderabad Telangana, India Kaizen SRA Technologies Private Limited Full time
Design Verification Engineer
Exp- 4+ years,
Location -HyderabadJoining Time- 30days,
• Development of UVM test benches and test cases for IPs.
• Debugging of test environment and design
• Creation of Scoreboards
• Refinement of assertions and coverage
• Advanced user of System Verilog
• Advanced user of UVM tools and methodology for IP verification.
• Experience with test development and test coverage assessment.
• Experience with setting up and running gate level simulations
• Develop and execute verification plans.



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