Design & Verification Engineer (PCIe/CXL)
4 weeks ago
We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow's idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow.
MED VTL Verification Group
We are seeking a skilled Verification Engineer to join our team. The successful candidate will be responsible for the verification of internally developed VTLs (Veloce-friendly standard protocols such as PCIe, CXL, SAS, Ethernet, MIPI, etc.) using various standard verification methodologies, including UVM, and ensuring signoff based on coverage matrix.
We are not looking for superheroes, just super minds
You're a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/VLSI from top reputed Engineering colleges with 4-8 years of significant experience in software development. Experience in EDA will be a phenomenal plus.
Practical experience with any of the following protocols: PCI/PCIe, SAS, Ethernet, MIPI.
Experience in IP and SOC level verification.
Knowledge of verification methodologies such as Specman, SV, UVM, OVM, TLM, Assertion, Coverage, co-simulation, and co-verification.
Good interpersonal skills for working with external interfaces.
FPGA/Emulation experience is helpful.
Strong scripting and automation knowledge is a significant plus.
Responsibilities:
At Siemens, we are always challenging ourselves to build a better future. We have some of the most inquisitive minds working across the world, re-imagining the future and doing outstanding things.
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