Senior Principal
3 weeks ago
Your journey will begin by spearheading the design and optimization of high-performance Active Electrical Cables (AECs), enhancing electrical integrity and signal quality across demanding link budgets.
Building on this foundation, you will architect and implement Ser Des technology tailored for PCIe 7.0, tackling challenges such as lane equalization, jitter tolerance, and power efficiency.
Finally, your work will expand into integrating cutting-edge optical interconnects and optocouplers, driving innovations in retimer technologies and hybrid signaling frameworks.This role directly impacts the performance and reliability of AI and cloud infrastructure—empowering massive data throughput, energy-efficient links, and scalable system architectures.Responsibilities:Lead the architecture and design of high-speed Ser Des for PCIe 7.0, targeting data rates of 128 GT/s and beyond.Spearhead the development and integration of advanced optical interconnects and retimer solutions within our Smart Cable Modules.Define and specify the requirements for mixed-signal Ser Des PHYs, including transmitter (TX), receiver (RX), and clock and data recovery (CDR) circuits.Conduct in-depth analysis and simulation of high-speed channel performance, including signal integrity (SI) and power integrity (PI).Collaborate with cross-functional teams, including hardware design, firmware, and system validation, to ensure successful product development and bring-up.Stay at the forefront of industry standards and emerging technologies, particularly related to PCIe, CXL, and high-speed optical interconnects.Mentor junior engineers and provide technical leadership across the organization.Work closely with partners and vendors to evaluate and select key components.Qualifications:Required Qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.10-20 years years of experience in high-speed Ser Des design and development.Proven expertise in PCIe protocols, with direct experience in PCIe 4.0/5.0/6.0 design and a strong understanding of the upcoming PCIe 7.0 specification.In-depth knowledge of mixed-signal design, including experience with PAM4 signaling, equalization techniques (e.g., FFE, DFE), and clocking architectures.Hands-on experience with high-speed test and measurement equipment (e.g., oscilloscopes, BERTs, VNAs).Strong understanding of signal integrity principles and experience with simulation tools (e.g., HSPICE, ADS, Ansys).Preferred Qualifications:Master's or Ph.
D.
in a relevant technical field.Experience with the design and integration of optical interconnects, silicon photonics, or high-speed optoelectronics.Familiarity with the design of retimers and their application in Active Electrical Cables.Experience with high-level modeling of Ser Des links using tools like MATLAB or Python.Knowledge of other high-speed protocols such as Ethernet, CXL, or NVLink.A track record of leading complex projects from concept to production.Excellent communication and interpersonal skills.Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"
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