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Senior Design Verification Engineer
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ASIC Design Verification
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Bengaluru, India L&T Technology Services Full timeJob Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve...
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Design Verification Engineer
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Design and Verification engineer
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Bengaluru, India L&T Technology Services Full timeJob description: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional...
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Design and Verification engineer
3 months ago
Bengaluru, India L&T Technology Services Full timeJob description: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional...
Design Verification
4 months ago
Job Description:Understanding the business requirements and functional specifications of the IPs, subsystems and SOC• Creating Verification Environment Architecture document• Reviewing and Revising: working towards meeting agreed upon acceptance criteria• Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification• Performing RTL simulations using Synopsys and Cadence simulators• Debugging and resolving problems found by simulations• Performance test plan development and maintenance• Development of transactors, monitors and models for performance verification• Implement performance verification flow including monitoring, synchronization, reporting and self-checking mechanisms• Provide full report of performance metrics and bottlenecks• Tracking tickets and code releases using Bug Tracking tool and GIT• Performing UPF (Unified Power Format) based Power Aware simulations• Coding of Assertion and Functional Coverage bins in SVA (System Verilog Assertions)• Code & Functional Coverage Closure• Performing Gate Level simulations• Preparing and conducting reviews of Verification Sign-off documents to ensure SOC tape-out quality
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