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Senior Design Verification Engineer

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Bengaluru, India Eximietas Design Full time
About Eximietas: a technology services and solutions company headquartered in San Jose, CA with a global footprint that extends to Bangalore, Chennai, and Bhubaneswar in India. Specializing in Cloud Computing, Cybersecurity, VLSI, Embedded Software, and Artificial Intelligence, Eximietas is dedicated to empowering businesses with cutting-edge innovations, ensuring their digital future is secure, efficient, and poised for growth. We foster a vibrant and collaborative work culture that thrives on innovation and inclusivity. Rooted in the spirit of Silicon Valley's tech dynamism, our global teams are united by a passion for excellence in technology and engineering.Job Overview:Job Title: Design Verification Engineer

We are seeking an experienced and highly skilled Senior Design Verification Engineer with a minimum of 4+ years of hands-on experience in Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs.

Job Description:

• Lead and manage Design Verification efforts for complex projects, ensuring the successful execution of verification plans.• Develop and implement comprehensive verification strategies, test plans, and test benches for high speed including low-speed peripherals like

I2C/I3C, SPI, UART, GPIO, QSPI, and high speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM.• Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.• Analyze and implement System Verilog assertions and coverage (code, toggle, functional).• Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.• Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.• Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.Experience with verification tools from Synopsys and Cadence, including

VCS and Xsim.• Integration of third-party

VIPs (Verification IP)

from

Synopsys and Cadence.

Qualifications:

• Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR Master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.• 4+ years of hands-on experience in Design Verification.• Expertise in

UVM (Universal Verification Methodology)

and

System Verilog .• Prior experience working on

IP level

and

SOC level v erification projects.• Proficient in verification tools such as

VCS, Xsim, waveform analyzers, and third party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).• Hands-on experience with

UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols .Solid understanding of

low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.• Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.• Proficiency in scripting languages such as shell, Makefile, and Perl.• Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.• C-System Verilog handshake and writing C test cases for bootup verification.Excellent problem-solving, analytical, and debugging skills