Senior RTL Design Engineer

2 days ago


Bangalore South, India ThunderSoft Full time

Senior RTL Design Engineer – PCIe Gen6/Gen5

Experience: 10+ Years

Location: Bangalore

Job Description:

Senior RTL Design Engineers for high-performance PCIe IP development. This is a critical role involving architecture, design, and delivery of next-generation PCIe interfaces.

Responsibilities

  • Design and implement RTL for PCIe Gen6/Gen5 IPs at block and subsystem level.
  • Develop micro-architecture, RTL coding, and integration of complex IP blocks.
  • Participate in timing analysis, lint, CDC checks, and synthesis flow.
  • Work closely with verification, validation, and physical design teams.
  • Contribute to technical reviews and documentation.

Required Skills:

  • 10+ years of hands-on RTL design experience, especially in complex IPs.
  • Mandatory: At least 1 year of experience in PCIe Gen6 design.
  • Strong knowledge of PCIe Gen6/Gen5 protocols, including MAC, PHY, and DL layers.
  • Proficiency in System Verilog/Verilog for RTL development.
  • Experience in using tools for synthesis, STA, lint, and CDC analysis.

Interested candidates can share resume to



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