Processor/firmware based verification, SV-UVM, RISC-V, 6-8 yrs

Hi All,Key Skills : SV-UVM, RISC-V, Processor/Firmware based verificationRequired experience : 6 to 8 yrsWork location : Hyderabad/ BangalorePlease share your resume to jayalakshmi.r2@ust.comRegards,Jaya

Hi All,Key Skills : SV-UVM, RISC-V, Processor/Firmware based verificationRequired experience : 6 to 8 yrsWork location : Hyderabad/ BangalorePlease share your resume to jayalakshmi.r2@ust.comRegards,Jaya

Hi All,Key Skills : SV-UVM, RISC-V, Processor/Firmware based verificationRequired experience : 6 to 8 yrsWork location : Hyderabad/ BangalorePlease share your resume to Regards,Jaya

Risc-V Design Verification Role at USTWe are seeking a skilled Risc-V design verification engineer to join our team at UST. This is an exciting opportunity for the right candidate to contribute to cutting-edge projects and grow their career.As a key member of our team, you will be responsible for designing and implementing verification environments for...

Hi All,Key Skills : SV-UVM, RISC-V, Processor/Firmware based verificationRequired experience : 6 to 8 yrsWork location : Hyderabad/ BangalorePlease share your resume to jayalakshmi.r2@ust.com Regards,Jaya

Job OverviewUST is a leading technology services company that partners with clients to help them succeed in a rapidly changing world. We are currently seeking a highly skilled Senior ASIC Design Verification Engineer to join our team.Key ResponsibilitiesDesign and develop verification environments for complex digital systems using SV-UVM.Collaborate with...

About UST:UST is a leading technology services company that helps organizations thrive in an increasingly complex business environment. Job Description:As a Senior ASIC Design Verification Engineer with expertise in RISC-V, you will play a key role in the development and verification of advanced semiconductor products. Key Responsibilities:Design and...

At UST, we are seeking an experienced RISC-V design verification engineer to join our team.Estimated Salary: ₹22 lakhs - ₹30 lakhs per annum (based on industry standards and location)Job Description:OverviewWe are a leading provider of end-to-end IT services and digital solutions. Our team of experts is dedicated to delivering high-quality solutions that...

We are Hiring for the below role - Position : CPU Verification (RISC-V/ARM) Location: Bangalore. Experience Required: 4+ Years. Key Skills and Responsibilities:  Experience into CPU Verification.  Strong in C/C++, ISA and Assembly Language.  Previous experience in Verification of embedded CPUs such as ARM/RISC-V/MIPS CPUs and interconnect...

Job Description:Talent Scout Management Solutions is seeking a Senior Verification Engineer to join our team.About the Role:The ideal candidate will have extensive experience in SystemVerilog (SV) and Universal Verification Methodology (UVM), with a strong background in developing and modifying UVM testbenches (TBs), creating and executing test plans, and...

About ACL DigitalWe are a leading technology company focused on innovative digital solutions.Job OverviewWe are seeking an experienced Senior Design Verification Engineer to join our team. This role will involve designing and implementing verification environments using SystemVerilog and UVM methodologies.ResponsibilitiesDevelop and execute verification...

: - 4+ years of design verification experience - 2+ years of OOP coding experience (System Verilog, SpecmanE or C++) and SV Assertions - Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM - Familiarity with Verilog and General Logic Design concepts - Knowledge of system-level architecture including buses like AXI/AHB/ACE/CHI and ARM...

We are seeking an experienced Senior Verification Engineer to join our team at Worc Consultancy Pvt Ltd.About the Role:As a Senior Verification Engineer, you will be responsible for developing and implementing verification environments using SystemVerilog (SV) and Universal Verification Methodology (UVM).Key Responsibilities:Design and develop verification...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologiesExperience in development of UVM based...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.8/10+ of hands-on experience in Stem Verilog/UVM methodology and/or C/C++ based verification8/ 10+ experience in IP/sub-stem and/or So C level verification based on Stem Verilog UVM/OVM based methodologiesExperience in development of UVM based...

Lead SOC Verification EngineerWe are seeking a skilled SOC Verification Engineer to join our team at ConnectPro Management Consultants Pvt Ltd. as a key member in the verification of advanced ARM-based SOCs.Job Summary:Lead and drive block, subsystems, and full-chip verification of advanced ARM-based SOCs.Architect and build test benches, reference models,...

JD for Design Verification Engineer5 to 18 years of hands-on DV experience in System Verilog/UVM.Must be able to own and drive the verification of a block / subsystem or a SOC.Extensive experience in IP/sub-system and/or So C level verification based on SV/UVM.Experience in Tesplan and Testbench development,Execution of test plan using high quality...

JD for Design Verification Engineer5 to 18 years of hands-on DV experience in SystemVerilog/UVM.Must be able to own and drive the verification of a block / subsystem or a SOC.Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.Experience in Tesplan and Testbench development,Execution of test plan using high quality constrained...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...