Senior design verification engineer

3 weeks ago

Bengaluru, Karnataka, India Hays Full time

Key Responsibilities:Develop, debug, and own System Verilog UVM-based testbenches for modem subsystemsDefine test plans from specs and drive testcase implementation end-to-endPerform RTL and netlist (gate-level) verificationRun regressions, analyze failures, and ensure functional & code coverage closureCollaborate with design and verification leads for issue resolutionRequirements: 7+ years of hands-on experience in SV UVM verification Strong ownership in modem/IP verification (4 G/5 G preferred) Experience in writing testcases from spec and driving regressions Expertise in both RTL and gate-level simulation Good debugging and scripting (Python/Perl) skills Nice to Have:Knowledge of wireless protocols (LTE/5 G)Experience with functional coverage closureExposure to DFT/low-power verification is a plus

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