Principal Engineer Verification

3 weeks ago


bangalore, India Infineon Technologies Full time
To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add.In your new role you will:
Candidate should have working experience with AMS Verification on multiple SOC’s or sub-systems.  Should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools.  Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus.  Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS).
Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus.  You are best equipped for this task if you have:
Bachelors with 13+ years or Masters with 12+ years of experience Technical mentoring for junior engineers. Instigate thought provoking culture Analog: Functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements

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