Principal Engineer
3 weeks ago
Experience Required:
5 - 15 Years
Job Term:
Permanent
Location:
Bangalore
Category:
Semiconductor Design
World leader in innovative memory solutions
Position Description:
• To be part of a highly skilled ASIC Team working on the newest technology nodes
• Responsible for Technically Leading an overall IP verification from test plan creation, UVM development to signoff
• Ensure first pass product through multi-dimensional verification coverage including mixed mode verification.
• Mentoring and coaching junior team members
• Pair with similar domain specialists across other geographical locations on core technical initiatives
SKILLS required:
• Good knowledge of DDR-PHY, LPDDR5/DDR4/5/HBM protocol
• Exposure to verification of complex high speed PHY and/or complex AMS IPs
• Proven track record of building testplan, UVM environment from scratch
• Experience with RTL debugging, score boarding and code coverage analysis
• Sound knowledge of System Verilog and UVM Methodology
• The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
• M.S./M.Tech, BS/BE (Electronics)
• Experience Required : 10+ Years
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