Pd emir engineer

Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Employment Type: Full-Time Are you passionate about Power Integrity, EM/IR signoff, and working on next-generation So C designs? ACL Digital company , is looking for talented and driven EMIR/PDN Engineers to be part of our world-class semiconductor design team in Bangalore...

Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Employment Type: Full-Time Are you passionate about Power Integrity, EM/IR signoff, and working on next-generation SoC designs? ACL Digital company , is looking for talented and driven EMIR/PDN Engineers to be part of our world-class semiconductor design team in...

Looking for EMIR Engineer Job location- Bangalore. Exp.-4+yrs Prefer- Immediate joiner or less notice period. Key Responsibilities: Perform IR drop and Electromigration (EM) analysis using tools like RedHawk SC, Voltus. Define EM/IR methodologies and flows. Collaborate with design teams to improve power grid design and robustness. Ensure...

Company: ACL Digital CompanyLocation: BangaloreExperience: 5 to 15 YearsEmployment Type: Full-TimeAre you passionate about Power Integrity, EM/IR signoff, and working on next-generation SoC designs?ACL Digital company, is looking for talented and driven EMIR/PDN Engineers to be part of our world-class semiconductor design team in Bangalore.Role &...

Hi All, Eximietas Hiring Senior Physical Design Leads/Managers (EMIR). Experience: 8+ Years. Location: Bengaluru. About the job Qualification Required: (EMIR). Block / Subsystem / Partition • Role: EM/IR. • EDA Tool: Redhawk & Node: TSMC 3nm / 5nm. • ESD resistance, PG Grid, Static/Dynamic power, SRP, BQM checks - Running/...

Hi All,Eximietas Hiring Senior Physical Design Leads/Managers (EMIR).Experience: 8+ Years.Location: Bengaluru.About the jobQualification Required: (EMIR).Block / Subsystem / Partition• Role: EM/IR.• EDA Tool: Redhawk & Node: TSMC 3nm / 5nm.• ESD resistance, PG Grid, Static/Dynamic power, SRP, BQM checks - Running/ Analysis/Fixes.• Tcl, Perl, Python...

LTTS is hiring for PD/STA Engineers with 7-10 years of experience.Job Location : BangaloreBelow is the job description...The PD/STA Engineer will be responsible for pre-design and static timing analysis tasks to ensure efficient silicon bring-up and product success. Day-to-day tasks include collaborating with design teams, performing timing analysis, and...

L& T Technology is looking to hire for Physical Design Engineers. Job Location : Bangalore Detailed JD is below :: JD for Pn R – 8+ ’ experience • IP/Block level Pn R activities from Netlist to GDS-II. • Good knowledge of all Pn R activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR...

So C DFT Engineer Job Description: Scan insertion. SCAN DRC/Coverage debug. ATPG Pattern generation. Gate level simulations ( Zero delay/Timing Delay simulations). Worked on JTAG/P1500 protocols. Perl/Tcl scripting. Timing/Formal verification/PD flow knowledge is plus. Location: Bangalore Notice Period: Immediate Experience: 5+ Years

Experience: 5 - 7 years as DFT Engineer Location: Bangalore Required Skills Scan insertion SCAN DRC/Coverage debug ATPG Pattern generation Gate level simulations ( Zero delay/Timing Delay simulations) Worked on JTAG/P1500 protocols Perl/Tcl scripting Timing/Formal verification/PD flow knowledge is plus