Design Verification Engineer- Uncore
3 weeks ago
About the Company
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
About the Role
Tenstorrent is looking for a Digital Design Verification Engineer to join our team. At Tenstorrent you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated team. We are looking for a DV Engineer to develop verification methodology for our products.
Responsibilities
- Define verification plans and develop DV environments independently in System Verilog (SV)/UVM.
- Knowledge of C++ is desirable.
- Create and execute test plans to ensure the quality and reliability of our IP solutions.
- Demonstrate expertise in System Verilog and UVM methodologies.
- Perform functional verification at the RTL level, including coverage analysis and improvement.
- Develop Universal Verification Components (UVCs) from scratch.
- Experience with Cache, NOC Interconnect verification is desirable.
- Knowledge of bus protocols like AXI, CHI etc. are added advantage.
Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
- 7+ years of proven experience in DV and verification methodologies.
- Strong proficiency in System Verilog and UVM.
- Ability to work independently and drive projects to completion.
- Excellent problem-solving and communication skills.
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