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Design Verification Engineer
2 months ago
Key Responsibilities:
Develop and execute comprehensive test plans for verification of complex digital designs.
Create and maintain #UVM -based verification environments.
Collaborate with design teams to identify and resolve issues early in the development process.
Contribute to functional coverage, code coverage, and debugging activities.
Participate in the verification of #ASIC / #FPGA / #SoC designs across various stages of development.
Skills & Qualifications:
Min 4+ years of experience with Design Verification.
Strong experience in design verification using #UVM , #SystemVerilog , or similar methodologies.
Expertise in writing #testbenches and #simulation .
Familiarity with tools like #VCS , #Questa , and other #EDA tools.
Solid understanding of #RTL design, verification metrics, and #debugging techniques.
Strong analytical and problem-solving skills.
Location: Multiple location Type: Full-time
Join us in shaping the future of semiconductors by ensuring the highest level of design quality