RTL Verification Engineer
2 months ago
Responsibilities:
- Develop and execute verification plans for complex digital RTL.
- Utilize the latest verification tools and methodologies, including UVM (Universal Verification Methodology), System Verilog, and formal verification techniques.
- Create and maintain testbenches, test cases, and verification environments.
- Create and automate regression flow.
- Perform functional coverage analysis and ensure comprehensive verification coverage.
- Debug and resolve design and verification issues in collaboration with design engineers.
- Participate in code reviews and provide feedback to improve design quality.
- Document verification processes, results, and methodologies.
Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 4 years of experience in digital RTL verification.
- Proficiency in SystemVerilog, UVM, and other verification methodologies.
- Experience with industry-standard verification tools such as Cadence, Synopsys, or Mentor Graphics.
- Strong understanding of digital design principles and RTL coding.
- Excellent problem-solving and debugging skills.
- Ability to work effectively in a team environment and communicate clearly with cross-functional teams.
- Knowledge in I2C/I3C, working with Analog team (developing Analog models), EEPROM interface, Interrupt Controller is a plus.
- Knowledge of scripting languages (e.g., Python, Perl) is a plus.
- Experience with formal verification techniques.
- Knowledge of low-power design and verification techniques.
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