Staff Verification with a Some Rtl Experience
3 months ago
**Job Requirements
**A new program started, it requires and RTL engineer with 8+ years of practical design and verification experience using SystemVerilog UVM and ASIC verification.
**Work Experience
**- Experience with Synopsys and/or Cadence simulation tools.
- RTL and possibly Gate level debug
Desireable Skills
- Experience with Synopsys and/or Cadence Synthesis, STA, DFT, Formal Equivalence tools.
- Experience with JIRA
- Knowledge of scripting languages such as Python or equivalent
- Knowledge of PLLs.
- Experience with mixed-signal design modelling and debugging.
Keywords
- UVM
- RTL
- SystemVerilog
- Synthesis
- Analog
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