Senior Design Verification Engineer

Design Verification Engineer OpportunityWe are seeking a skilled Design Verification Engineer to join our dynamic team. This role offers an exciting chance to work on senior design verification projects, utilizing your expertise in UVM/SV.

About CompanyEspressif Systems (688018) is a public multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power IoT solutions. We...

About Company Espressif Systems (688018) is a public multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power IoT solutions. We...

Tips: UVM, Design Verification.ResponsibilitiesDevelop UVM interface agents from scratch and integrate them into the testbench.Develop sequences, testcases, functional coverage as per testplan.Develop testplan by reading the specification in detail, present to the verification and design teams.Understand the existing complex testbench and update it to add...

JD Design Verification• Understanding the business requirements and functional specifications of the IPs, subsystems and SOC• Creating Verification Environment Architecture document• Reviewing and Revising: working towards meeting agreed upon acceptance criteria• Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit,...

7+ experience in verification with strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodologyExperience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPISolid understanding of digital hardware design and Verilog HDL.Detailed understanding and experience of the current...

7+ experience in verification with strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodologyExperience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPISolid understanding of digital hardware design and Verilog HDL.Detailed understanding and experience of the current...

1. 7+ experience in verification with strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology2. Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI3. Solid understanding of digital hardware design and Verilog HDL.4. Detailed understanding and experience of the...

7+ experience in verification with strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodologyExperience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPISolid understanding of digital hardware design and Verilog HDL.Detailed understanding and experience of the current...

1. 7+ experience in verification with strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology2. Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI3. Solid understanding of digital hardware design and Verilog HDL.4. Detailed understanding and experience of the...