Senior verification engineer

Senior Verification Engineer - Location: Bangalore/Hyderabad - Experience: 4+ years - 1Must have very good System Verilog/UVM experience - Must have expertise in PCI gen6 and CXL3.1or Ethernet bus protocols - Have experience in IP/SoC Verification - Expertise in AMBA/AXI bus protocols and ARM CPU - Experience in developing functional verification...

Job Description: Design Verification Engineer (Senior Level - 5+ years’ experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and So C projects. This senior-level position demands a mastery of verification...

Job Title: Senior Design Verification Engineer Location: Bengaluru, India Experience: 5+ Years Notice Period: Less than 30 Days Job Description: We are seeking a Senior Design Verification Engineer with 5+ years of experience in So C/IP level verification . The candidate must have strong expertise in System Verilog, UVM methodology , testbench...

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ Ahmedabad ROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans. Relevant experience with one or more of PCIe, NVMe, NAND,...

Senior Verification EngineerLocation: Bangalore/HyderabadExperience: 4+ years1Must have very good System Verilog/UVM experienceMust have expertise in PCI gen6 and CXL3.1or Ethernet bus protocolsHave experience in IP/SoC VerificationExpertise in AMBA/AXI bus protocols and ARM CPUExperience in developing functional verification environments including the...

Senior Design verification Engineer Mandatory Skill : PCIE Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Coverage: Achieve functional and code coverage targets through constrained random and directed...

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ Ahmedabad ROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans. Relevant experience with one or more of PCIe,...

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

Senior Design Verification Engineer: Should have PCIE IP level verification exposure Good UVM understanding Serial protocol understanding Interested,please drop your updated CV to

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ AhmedabadROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches.Highly experienced with defining block, sub-system and SOC top level test plans.Relevant experience with one or more of PCIe, NVMe, NAND, DDR and...