RTL Release Principal Design Engineer
1 week ago
Job Summary:
We are seeking a highly skilled Electronics Engineer or Computer Engineer with 7-10 years of experience to join our team. The ideal candidate will have a strong background in RTL design flow steps, including RTL coding, simulation, compilation/testbench validation, synthesis, timing, DFT, lint, CDC, LEC, and more.
Key Responsibilities:
- Debug existing Verilog/System verilog test cases with minimal supervision
- Perform functional simulation using Verilog/System Verilog
- Develop skills in scripting languages (Shell, Perl, TCL, Python) for automation and design database qualification
- Familiarity with Power Flow (UPF/CPF)
- Collaborate with IP-development teams to ensure high-quality releases
- Maintain project timelines and manage multiple high-priority projects
- Bug reporting and resolution closure with IP providers
- Debug synthesis/timing analysis constraints, reports, logs
- Leverage new tools/flows and develop methodology as needed
- BUILD STRONG RELATIONSHIPS WITH DESIGNERS AND APPLICATION ENGINEERS
Additional Desirable Qualifications:
- Familiarity with SerDes/DDR/other Design-IP's & Analog design flows
- Familiarity with IP release and tracking management systems
Requirements:
- College education in Electronics Engineering or Computer Engineering
What We Offer:
- A fast-paced environment with opportunities for growth and development
About Us:
We are a dynamic company that values innovation, collaboration, and teamwork. We offer a competitive compensation package and opportunities for professional growth and development.
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