Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. MTS SILICON DESIGN ENGINEER THE ROLE: As an MTS Design Verification Engineer in AMD’s Infinity (Data) Fabric team, you will be a technical engineer responsible for driving verification of high-performance, scalable fabric IP that connects compute, memory, and I/O subsystems across AMD’s CPUs, GPUs, and APUs. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Own verification execution for complex Data Fabric IP blocks and subsystems from spec review through tape-out. Lead test plan creation and sign-off, integrating both constrained-random and directed testing methodologies. Drive coverage-driven verification — define, track, and close both functional and code coverage goals. Collaborate cross-functionally with design, architecture, and performance teams to debug complex issues and ensure first-pass silicon success. Mentor and guide junior and mid-level verification engineers, reviewing their code, test plans, and coverage results Identify and drive verification methodology improvements, automation, and process optimizations to enhance team productivity. Participate in post-silicon debug and validation, assisting in recreating and root-causing issues found in lab or customer systems PREFERRED EXPERIENCE: Expertise in System Verilog & UVM for block- and system-level verification of complex IP. Proven track record of leading verification on large, high-performance ASICs or SoCs from concept to tape-out. Strong knowledge of computer architecture and interconnect/fabric protocols. Proficiency in EDA tools such as Synopsys VCS Advanced debug skills for simulation and waveform analysis. Scripting proficiency in Python, Perl, or similar for automation and flow development. Experience with coverage closure strategies, regression management, and verification metrics reporting. Familiarity with formal verification concepts and tools is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.MTS SILICON DESIGN ENGINEER THE ROLE: As an MTS Design Verification Engineer in AMD’s Infinity (Data) Fabric team, you will be a technical engineer responsible for driving verification of high-performance, scalable fabric IP that connects compute, memory, and I/O subsystems across AMD’s CPUs, GPUs, and APUs. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Own verification execution for complex Data Fabric IP blocks and subsystems from spec review through tape-out. Lead test plan creation and sign-off, integrating both constrained-random and directed testing methodologies. Drive coverage-driven verification — define, track, and close both functional and code coverage goals. Collaborate cross-functionally with design, architecture, and performance teams to debug complex issues and ensure first-pass silicon success. Mentor and guide junior and mid-level verification engineers, reviewing their code, test plans, and coverage results Identify and drive verification methodology improvements, automation, and process optimizations to enhance team productivity. Participate in post-silicon debug and validation, assisting in recreating and root-causing issues found in lab or customer systems PREFERRED EXPERIENCE: Expertise in System Verilog & UVM for block- and system-level verification of complex IP. Proven track record of leading verification on large, high-performance ASICs or SoCs from concept to tape-out. Strong knowledge of computer architecture and interconnect/fabric protocols. Proficiency in EDA tools such as Synopsys VCS Advanced debug skills for simulation and waveform analysis. Scripting proficiency in Python, Perl, or similar for automation and flow development. Experience with coverage closure strategies, regression management, and verification metrics reporting. Familiarity with formal verification concepts and tools is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-BM2Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.