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Silicon Formal Verification Engineer
1 month ago
Silicon Formal Verification Engineer :-
Bangalore
Founded in 2023,by Industry veterans HQ in California,US
- We are revolutionizing sustainable AI compute through intuitive software with composable silicon
Silicon Formal Verification Engineer
• Job Description
o In this role you will be responsible for developing and applying formal
verification techniques to ensure functional correctness and completeness of
Tsavorite's high performance AI/ML Chiplet and SiP products.
o You will collaborate with a team of highly skilled team Architects and RTL Design
engineers to identify, define, and verify components suited for formal analysis.
o Create robust formal abstract models to verify system-level properties, such as
deadlocks, livelocks, anti-starvation, coherency.
o Innovate by integrating formal methods with simulation-based techniques to
enhance bug detection efficiency.
o Develop scalable and reusable proof methodologies to support the verification
process.
• Technical Requirements
o In-depth knowledge in formal verification algorithms, methods and use cases
o Expert user of formal verification tools (JasperGold, VC Formal, Questa Formal
tools)
o Expertise in system Verilog assertion and abstract model development
o Hands on experience as Formal verification Engineer on AI or CPU designs.
o Comprehensive knowledge of computer architecture and familiarity with x86 or
ARM or RISC processors:-
• Job Description
o In this role you will be responsible for developing and applying formal
verification techniques to ensure functional correctness and completeness of
Tsavorite's high performance AI/ML Chiplet and SiP products.
o You will collaborate with a team of highly skilled team Architects and RTL Design
engineers to identify, define, and verify components suited for formal analysis.
o Create robust formal abstract models to verify system-level properties, such as
deadlocks, livelocks, anti-starvation, coherency.
o Innovate by integrating formal methods with simulation-based techniques to
enhance bug detection efficiency.
o Develop scalable and reusable proof methodologies to support the verification
process.
• Technical Requirements
o In-depth knowledge in formal verification algorithms, methods and use cases
o Expert user of formal verification tools (JasperGold, VC Formal, Questa Formal
tools)
o Expertise in system Verilog assertion and abstract model development
o Hands on experience as Formal verification Engineer on AI or CPU designs.
o Comprehensive knowledge of computer architecture and familiarity with x86 or
ARM or RISC processors
Contact:
Uday
Mulya Technologies
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