Mulya Technologies | Senior Physical Design Manager | hyderabad
1 week ago
Full-chip DesignStart-up experienceMust be Hands-on
You will work with an elite team of physical design implementation engineers and have personal design responsibility, including synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management.
ResponsibilitiesWork at various levels of implementation of hierarchical chip (Blocks and Top)Floor plan and partition, power plan, bump planIntegration of different sub-blocks and custom macros/IPsPhysical implementation of blocksBlocks and top-level timing IR analysis and closurePhysical VerificationDevelop, support and maintain physical design flows and methodologiesRequirementsB.Tech / M.Tech from a reputed university with 10-15+ years of experience.Good knowledge of VLSI process and device characteristics.Experience doing physical design targeted to the 3nm / 5nm/7nm FinFet process.Good knowledge of cell libraries various views and models.Good understanding of static timing analysis (STA), EM/IR and sign-off.Strong hands-on experience with: Chip Level / Sub-chip level floor planning, partition, pin assignment, Power planning, Bump Planning, Pad Ring Creation, Block level physical implementation, timing closure, physical verification, Chip level integration of different sub-blocks and custom macros/IPs, Timing, IR/EM analysis and closure, Physical Verification – block and chip level.EDA Tool Expertise: Innovus, Tempus/PrimeTime-SI, Voltus/RedHawk, StarXT/Quantus, Calibre,LEC etc.Good software and scripting skills (Python, tcl).Good communication skills and the ability and desire to work as part of a team.Self-driven individual and an excellent team player.Good communication abilities.
Contact:UdayMulya "Mining The Knowledge Community"
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Senior physical design manager
1 week ago
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