Mulya Technologies | Senior Verification Manager
5 hours ago
Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad
Senior Design Verification Manager
Hyderabad
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Role Overview:
As the Senior Design Verification Manager, you will lead the verification team responsible for ensuring that our semiconductor designs meet functional, performance, and quality specifications. You will define and implement the verification strategy, develop advanced verification environments, and drive the verification process from specification through to tape-out. This role requires close collaboration with cross-functional teams, including architecture, RTL design, and physical design, to ensure that all design features and constraints are verified thoroughly.
Key Responsibilities:
- Team Leadership:
- Lead, mentor, and manage a team of design verification engineers.
- Develop and implement best practices for functional verification and test plan execution.
- Provide technical guidance and hands-on support to the team throughout the verification lifecycle.
- Verification Strategy & Planning:
- Define and drive the verification strategy and methodology for complex SoC and ASIC designs.
- Create verification plans based on design specifications and architecture documents.
- Define milestones and ensure verification activities are completed on schedule.
- Verification Environment Development:
- Develop and maintain UVM-based (Universal Verification Methodology) verification environments.
- Implement directed, random, and constrained-random test cases to ensure complete coverage of design functionality.
- Develop automated testbenches, monitors, checkers, and scoreboard modules.
- Functional & Performance Verification:
- Lead functional verification, power verification, and formal verification activities.
- Perform RTL simulations, waveform analysis, and debug to verify design correctness.
- Ensure verification coverage metrics, such as code coverage, functional coverage, and assertion coverage, meet the required thresholds.
- Collaboration & Communication:
- Collaborate with RTL designers, architects, and physical design engineers to ensure the smooth handoff between design and verification.
- Communicate verification progress, issues, and risks to senior management and key stakeholders.
- Manage external verification vendors and partners, as needed, to meet project timelines.
Required Qualifications:
- Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field.
- 12-18 years of experience in SoC/ASIC/FPGA verification, with at least 3+ years in a leadership or managerial role.
- Extensive experience with UVM, SystemVerilog, and developing advanced verification environments.
- Hands-on experience with RTL design verification, functional coverage, and code coverage tools.
- Proven expertise in simulation tools such as Cadence Xcelium, Synopsys VCS, Mentor Questa, or equivalent.
- Strong knowledge of scripting languages (e.g., Perl, Python, TCL) for automating verification tasks.
- Familiarity with industry-standard protocols (e.g., PCIe, DDR, Ethernet) and processor-based designs.
- Strong debugging skills and a methodical approach to problem-solving.
Preferred Qualifications:
- Experience in a startup environment or fast-paced semiconductor industry.
- Familiarity with low-power design techniques and formal verification tools.
- Experience working with hardware emulation platforms (e.g., Palladium, Zebu, or FPGA prototyping).
- Familiarity with DFT (Design for Testability) and post-silicon validation techniques.
- Knowledge of silicon bring-up and lab-based verification.
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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