RTL to GDSII Engineer
4 weeks ago
Location: Bangalore
Notice Period: Immediate to 15 Days
We are seeking experienced RTL to GDSII Engineers with a minimum of 5 years of relevant experience to join our team in Bangalore. The ideal candidate will possess strong technical expertise in synthesis and timing analysis, with hands-on experience across the complete RTL to GDSII flow.
Key Responsibilities:
- Develop and maintain Design Compiler (DC) constraint files
- Perform Pre-Timing Synthesis on RTL designs
- Execute Pre-Static Timing Analysis (Pre-STA) and support Physical Design (PD) activities
- Collaborate with cross-functional teams to achieve design closure and ensure high-quality deliverables
Required Skills & Experience:
- 5+ years of experience in RTL to GDSII design flow
- Strong background in synthesis, STA, and physical design processes
- Hands-on expertise in writing DC constraint files
- Proven ability to debug and resolve design and timing issues
- Availability to join within 15 days
If you meet the above qualifications and are looking for a challenging opportunity in a dynamic environment, we encourage you to apply.
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Bengaluru, India Sintegra Inc. Full timeJob SummaryWe are seeking a highly experienced Senior Physical Design Engineer with a minimum of 10 years in the RTL to GDSII flow. This role requires hands-on expertise with Cadence Innovus , experience at N3 and below process nodes , and strong scripting and flow debugging skills .Key ResponsibilitiesLead physical design activities from RTL to GDSII,...
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Bengaluru, India Sintegra Inc. Full timeJob SummaryWe are seeking a highly experienced Senior Physical Design Engineer with a minimum of 10 years in the RTL to GDSII flow. This role requires hands-on expertise with Cadence Innovus, experience at N3 and below process nodes, and strong scripting and flow debugging skills. Key ResponsibilitiesLead physical design activities from RTL to GDSII,...
