Verification Engineer
1 month ago
Job DescriptionThe position involves design verification of next generation modem sub systems (which has MAC, Baseband and RF IP’s involved for latest Wi-Fi protocol including 11ax) with emphasis on verifying and signing off performance and power along with functionality. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS and Formal techniques. Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. He/She will work with design team (both HW and SW) on RTL debug during Pre-silicon HW development phase.
Responsibilities:Develop and track execution of chip level test planning to meet product requirements and established quality standardsLead a team to complete the pre-silicon verification of an SoCExecute and maintain chip level verification regressions. Triage and debug failing tests.Develop or update tests to satisfy the test plan requirements. Tests will be combination of directed (C tests), constrained random (UVM), and formal verification.Perform gate level verification across corners. Provide appropriate activity files for power analysis.Coordinate verification activities with a global team and the design lead. Provide succinct weekly status and drive action items to closure.
Experience Level
:
6-14 years in Industry
Education Requirements:
Bachelor or Master’s degree in Electrical and/or Computer Engineering
Minimum Qualifications:Architect Block and SS Level Test-BenchesUnderstanding of WLAN PHY TX and RX design paths,Algorithms that control the various aspects of wireless systemsDevelop test plan to verify WiFi Standards including 11ax ,sequences and design components.Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goalsExplore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benchesStrong knowledge of Verilog, System Verilog, UVM, C/C++Experience in usage of assertions, constrained random generation, functional/code coverage.Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flowsAnalytical debugging skillsVerify and debug low-power designDebug SDF Back Annotated Gate SimulationsLow-power implementation (UPF)Mixed Signal Real Number Modeling (RNM, Spice)
Preferred Qualifications:Knowledge of wireless technologies like WLAN – 11ax , Bluetooth, ZigBeeMentoring skillsExceptional problem-solving skillsGood written and oral communication skills
Benefits & Perks :Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.Equity Rewards (RSUs)Employee Stock Purchase Plan (ESPP)Insurance plans with Outpatient coverNational Pension Scheme (NPS)Flexible work policyChildcare support
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
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