Staff/sr. staff system ip design verification engineer
13 hours ago
We're looking for a passionate and hands-on RISC-V System IP DV Engineer to architect, develop, and evolve world-class verification infrastructure for System IPs (interrupt controllers, IOMMU, power management, DFD etc) that will be integrated in high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are You bring domain understanding of memory management at core/system level, concepts like virtual/physical memory, page tables etc You thrive in building robust verification environments using System Verilog and UVM, and optionally C++, and can define and drive verification plans independently. You have a strong grasp of stimulus planning, checker development, debug techniques, and coverage closure for verifying complex hardware subsystems. You’re comfortable working on features that span multiple IPs and can devise plans to verify them at IP, subsystem and fullchip levels. What We Need A Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. 7 - 15 Years of Strong experience with System Verilog and UVM-based verification. Proven ability to drive IP level and subsystem level DV projects. Familiarity with core MMU or SMMU/IOMMU, bus protocols like AXI. What You Will Learn Owning a large scope with a small focused team. How to structure and deliver a configurable IP to So Cs with seamless integration in mind. How IOMMU can be integrated in a So C, collaborating closely with RTL designers, architects etc. Building reusable verification components, coverage models, and checkers that scale across multiple abstraction layers.
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Bangalore, India Tenstorrent Full timeWe're looking for a passionate and hands-on RISC-V System IP DV Engineer to architect, develop, and evolve world-class verification infrastructure for System IPs (interrupt controllers, IOMMU, power management, DFD etc) that will be integrated in high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating...
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Bangalore, India Tenstorrent Full timeWe're looking for a passionate and hands-on RISC-V System IP DV Engineer to architect, develop, and evolve world-class verification infrastructure for System IPs (interrupt controllers, IOMMU, power management, DFD etc) that will be integrated in high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and...
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Bangalore, India Tenstorrent Full timeWe're looking for a passionate and hands-on RISC-V System IP DV Engineer to architect, develop, and evolve world-class verification infrastructure for System IPs (interrupt controllers, IOMMU, power management, DFD etc) that will be integrated in high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and...
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bangalore, India Tenstorrent Full timeWe're looking for a passionate and hands-on RISC-V System IP DV Engineer to architect, develop, and evolve world-class verification infrastructure for System IPs (interrupt controllers, IOMMU, power management, DFD etc) that will be integrated in high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with...
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Verification Lead Design Engineer
5 days ago
bangalore, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...
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Sr Principal PD Design Engineer
20 hours ago
bangalore, India Cadence System Design and Analysis Full timeThis is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing,...
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Staff Design Verification Engineer
3 days ago
Bangalore, Karnataka, India Analog Devices Full timeAbout Analog DevicesAnalog Devices Inc NASDAQ is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge ADI combines analog digital and software technologies into solutions that help drive advancements in digitized factories mobility and digital healthcare combat climate change ...
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Design verification engineer
13 hours ago
Bangalore, India ACL Digital Full timeDesign Verification Engineer - Senior / Lead / Sr. Lead Job Description: Must have good knowledge on the verification flows. Excellent hands-on debug skills and problem solving attitude.. Experience of working in complex test-bench/model in Verilog, System Verilog or System C Experience of working on Functional Verification, So C Verification, Emulation...
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Sr RTL Principal Design Engineer
5 days ago
bangalore, India Cadence System Design and Analysis Full timeRTL Design Engineer for Interface Controller IP development team.Position is based in Bangalore or Noida.The role would include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence.The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as...
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Senior/staff/sr staff design verification engineer
13 hours ago
Bangalore, India Synopsys Inc Full timeJob description In this role, you will be creating UVM testbenches for a So C and IP, as well as tests, regressions, and functional coverage to achieve zero bug escapes. You will interface with the designers to develop the test plans, and from that develop testcases and coverage to thoroughly verify the RTL. Your regressions will grow to cover the full...
