Senior ASIC Front End Implementation Engineer

3 weeks ago


Bengaluru, Karnataka, India Sintegra Inc. Full time
  • Perform RTL synthesis using industry-standard tools (Synopsys DC/Genus/Fusion Compiler or equivalent).
  • Develop and maintain synthesis scripts, flows, and methodology to ensure repeatable, high-quality results.
  • Create and validate timing constraints (SDC) for block and top-level synthesis.
  • Collaborate with RTL design engineers to ensure coding styles are synthesis-friendly and optimize for area, power, and performance.
  • Conduct linting, formal checks, and equivalence checking (LEC) to ensure correctness of synthesized netlists.
  • Support early design exploration (area, power, timing trade-offs) and provide feedback to architecture and RTL teams.
  • Work closely with physical design teams to ensure clean handoff, focusing on timing closure and constraint alignment.
  • Debug and resolve synthesis and timing issues across hierarchical and flat design contexts. Automate


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