Senior Layout Engineer
1 week ago
We are a leading innovator in the semiconductor industry, specializing in cutting-edge Analog and RF solutions.
Job Overview:
As a Senior Layout Engineer specializing in Analog/RF , you will play a pivotal role in the physical design and verification of custom Analog/RF mixed-signal integrated circuits. Your responsibilities will encompass IC mask layout design, physical verification, and collaboration with cross-functional teams to ensure the successful development of high-quality semiconductor products.
Join our dynamic team and contribute to cutting-edge advancements in Analog and RF technologies
Key Responsibilities:
• Perform IC mask layout design and physical verification for custom Analog/RF mixed signal, IO & ESD designs at the Block/Module level.• Execute and oversee layout activities, including LVS/DRC/antenna checks, for complex mixed-signal integrated circuits.• Collaborate closely with circuit designers and CAD engineers to create and optimize custom Analog mixed-signal block layouts.• Ensure adherence to established companywide layout design & CAD methodologies and process flows.• Lead and manage a team of 4-5 professionals, providing guidance and support as necessary, and contributing individually when required.• Identify and resolve issues related to the failure-prone circuit and layout structures, working in tandem with circuit designers to find optimal solutions.• The candidate should have worked on higher nodes 28nm/40nm & above• We DO NOT need candidates who have worked on lower nodes like 3nm/4nm/8nm etc
Essential Requirements:
• Bachelor's degree in a technology-related field with a minimum of 8 - 12 years of relevant experience in layout engineering for Analog/RF domains. Candidates from premier institutes are preferred for all experience levels.• Proficiency in Transistor level floor planning within a multi-voltage, mixed-signal, high-speed, and noise-sensitive environment.• Extensive experience with tools such as Cadence Virtuoso-XL, Virtuoso-L, Mentor Graphic Calibre, Cadence Assura/PVS, and Linux Operating System.• Strong expertise in interpreting and addressing caliber/Assura DRC, LVS, ERC, antenna, and post-layout extraction issues.• In-depth knowledge of Analog layout techniques, CMOS fabrication concepts, and processes.• Excellent communication skills, both verbal and written, with proficiency in creating documents using Microsoft Office and Microsoft PowerPoint.• Familiarity with Latch-up prevention, ESD protection schemes, and an understanding of issues related to RC delay, electromigration, and cross-capacitance.
Contact:UdayMulya "Mining The Knowledge Community"
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