Principal Design Verification Engineer
1 month ago
You will be part of a Verification Team.You will be responsible for driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases.You will be responsible for analysing Code Coverage, Functional Coverage and Assertions.Use industry standard tools, methodologies.Solid experience in verification of complex SoCs.Expertise in SoC Verification using SV and Verilog. Knowledge of UVM is a plus.Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification.Verification experience in complex datapath, DSP based ASICs is highly desirable.Good knowledge in gate-level simulation, and Scripting languages like Python, TCL.Excellent debugging and problem solving skills.Strong communication skills.Education and Experience
B.E./B.Tech./M.E./M.Tech in VLSIMinimum of 8 years of working experience in Digital Verification/Formal Verification flow of a product company.Candidate must have working experience System Verilog/UVM based verification flow.
We are looking for trailblazers ...
We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem.
we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition.
If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us.
We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence.
Contact:UdayMulya
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