Current jobs related to Senior Physical Design Engineer - hyderabad - MosChip®

  • Senior Physical Design Engineer

    1 week ago

    hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/Lead Location: Bangalore, Hyderabad, Noida and Ahmedabad Experience Required: 4+ ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity,...

  • Senior Physical Design Engineer

    3 weeks ago

    Hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 4+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...

  • Senior Physical Design Engineer

    3 weeks ago

    Hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 4+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...

  • Senior Physical Design Engineer

    1 week ago

    hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 4+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...

  • Senior Physical Design Engineer

    3 weeks ago

    Hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/Lead Location: Bangalore, Hyderabad, Noida and Ahmedabad Experience Required: 4+ ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal...

  • Senior Physical Design Engineer

    3 weeks ago

    Hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 4+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...

  • Senior Physical Design Engineer

    4 days ago

    hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff Engineer Skills required: Job Title: Physical Design Lead (6 to 15 years ) Job Descriptio n : In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have...

  • Senior Physical Design Manager

    1 day ago

    hyderabad, India Mulya Technologies Full time

    Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad Senior Physical Design Manager ================ Senior Physical Design Manager #### **Job Summary:** We are seeking a highly experienced, hands-on and motivated Physical Design Manager to lead our physical design team. The...

  • Senior Physical Design Manager

    4 days ago

    Hyderabad, India Mulya Technologies Full time

    Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / HyderabadSenior Physical Design Manager================Senior Physical Design Manager#### **Job Summary:**We are seeking a highly experienced, hands-on and motivated Physical Design Manager to lead our physical design team. The ideal...

  • Senior Physical Design Engineer

    4 days ago

    hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff EngineerSkills required: Job Title: Physical Design Lead (6 to 15 years) Job Description: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on...

  • Senior Physical Design Engineer

    4 days ago

    Hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff Engineer Skills required: Job Title: Physical Design Lead (6 to 15 years ) Job Descriptio n :In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have...

  • Senior Physical Design Engineer

    4 days ago

    Hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff EngineerSkills required: Job Title: Physical Design Lead (6 to 15 years) Job Description: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on...

  • Senior Physical Design Engineer

    4 days ago

    Hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff EngineerSkills required: Job Title: Physical Design Lead (6 to 15 years) Job Description: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on...

  • Senior Physical Design Engineer

    1 week ago

    hyderabad, India MosChip® Full time

    Responsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Worked on 65nm or lower node...

  • Senior Physical Design Engineer

    4 weeks ago

    hyderabad, India MosChip® Full time

    Responsibilities:Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.Worked on 65nm or lower node...

  • Senior Physical Design Engineer

    4 weeks ago

    Hyderabad, India MosChip® Full time

    Responsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.Worked on 65nm or lower node...

  • Senior Physical Design Engineer

    1 week ago

    hyderabad, India MosChip® Full time

    Responsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.Worked on 65nm or lower node...

  • Senior Physical Design Engineer

    4 weeks ago

    Hyderabad, India MosChip® Full time

    Responsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Worked on 65nm or lower node...

  • Senior Physical Design Engineer

    4 weeks ago

    Hyderabad, India MosChip® Full time

    Responsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.Worked on 65nm or lower node...

  • Senior Physical Design Engineer

    16 hours ago

    Hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff EngineerSkills required:Job Title: Physical Design Lead (6 to 15 years)Job Description:In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on...

Senior Physical Design Engineer

4 months ago

hyderabad, India MosChip® Full time
He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
· Provide technical guidance, mentoring to Physical Design Engineers.
· Interface with front-end ASIC teams to resolve issues.
· Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
· Timing closure on DDR2/DDR3/PCIE interfaces.
· Excellent communication skills.
· Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
· Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
· Expertise in scripting languages such as PERL, TCL.
· Strong Physical Verification skill set.
· Static Timing Analysis in Primetime or Primetime-SI.
· Good written and oral communication skills. Ability to clearly document plans.
· Ability to interface with different teams and prioritize work based on project needs.
Experience – 4 to 8 Years
Location: Hyderabad