Mixed Signal ASIC Design

2 weeks ago

Pune, India VASBEAM Pvt Ltd Full time
Job Description:·

Lead and coordinate a team of 5 engineers in mixed-signal, RF, analog and digital domain·

Design and guide projects on

advanced mixed-signal circuits data converters, sub-sampling phase locked loops, serdes and RF circuits in CMOS and BiCMOS and low-power & low-voltage applications.·

Skilled in Cadence custom IC EDA tools. Knowledge of Keysight Pathway desired.Achieve successful realization of the layout in close collaboration with layout team.·

Work with application developers to co-develop hardware and software systems.Collaborate with teams in India and abroad during project implementation phase.Requirements:PhD/Master degrees from top universitiesMust have a

Proven track record

of taking multiple mixed-signal ICs through the entire development cycle, from concept to production.+ 10 years’ experience

industrial experience in analog and mixed-signal design.Successful realization of more than 5 ASIC designsIn depth knowledge of Cadence custom IC EDA toolsProficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS.Experience with HDL languages Verilog and/or VHDL is desired.Scripting skills: Python, Perl and C is a plus.·

Experience with design, implementation, and development environments for reconfigurable systems (such as FPGAs) is a plus.·

Experience with the silicon manufacturers and working with various CMOS process technologies is a plus.

Experience:

10 years + relevant industry experienceDesired Aptitudes:·

Ability to work and manage high performance team.·

One who is individual contributor to the success of the team.·

Ability to adapt to a diverse customer base and willingness to undertake periodic local.·

Travel to customer sites·

Aptitude for learning new technologies and applications·

Good writing, verbal and interpersonal communication skills·

Competent in developing solutions as well as identifying problems·

Knowledge of production processes to ensure quality and robustness

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