AMS Verification Engineer

AMS Verification Engineer / Lead- Skills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scripting- BE/B.Tech in ECE /M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal Verification- Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks- Very...

AMS VerificationExperience Level : 6-18 years in IndustryResponsibilities :- To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs.- Leading a project for AMS requirements is a value add.- Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools- Knowledge of digital design techniques, Verilog...

AMS VerificationExperience Level : 6-18 years in IndustryResponsibilities :- To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs.- Leading a project for AMS requirements is a value add.- Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools- Knowledge of digital design techniques, Verilog...

AMS VerificationExperience Level : 6-18 years in IndustryResponsibilities :- To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs.- Leading a project for AMS requirements is a value add.- Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools- Knowledge of digital design techniques, Verilog...

AMS VerificationExperience Level : 6-18 years in IndustryResponsibilities :- To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs.- Leading a project for AMS requirements is a value add.- Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools- Knowledge of digital design techniques, Verilog...

AMS VerificationExperience Level : 6-18 years in IndustryResponsibilities :- To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs.- Leading a project for AMS requirements is a value add.- Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools- Knowledge of digital design techniques, Verilog...

Skills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scripting  Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks · Very Good experience in Analog Mixed Signal verification simulation tools · Good experience in System Verilog, UVM methodologies...

AMS Verification Engineer / Lead- Skills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scripting- BE/B.Tech in ECE /M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal Verification- Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks- Very...

Skills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scriptingBE/B.Tech in ECE /M.Tech in VLSI with 9 years experience in Analog Mixed Signal VerificationVery Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocksVery Good experience in Analog Mixed Signal...

Skills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scriptingBE/B.Tech in ECE /M.Tech in VLSI with 9 years experience in Analog Mixed Signal VerificationVery Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocksVery Good experience in Analog Mixed Signal...

Skills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scriptingBE/B.Tech in ECE /M.Tech in VLSI with 9 years experience in Analog Mixed Signal VerificationVery Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocksVery Good experience in Analog Mixed Signal...

Skills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scripting BE/B.Tech in ECE /M.Tech in VLSI with 9 years experience in Analog Mixed Signal Verification Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks Very Good experience in Analog Mixed Signal...

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Exp - 4+ yrsLocation - HyderabadKey Responsibilities:Develop and execute verification plans for analog and mixed-signal integrated circuits, ensuring compliance with design specifications and performance requirements.Design and implement test benches, test cases, and verification methodologies using industry-standard tools and languages.Collaborate with...

Tips: Provide a summary of the role, what success in the position looks like, and how this role fits into the organization overall.ResponsibilitiesNeed verification engineers with solid verification experience(7-8+ year) at IP or SOC levelGood experience in SV/UVM based testbench creation, test case writing, checkers, monitors, debugs, coverage analysis.GLS,...

Job Description:Roles & Responsibilities:Exp- 12 - 16 yrsThe role requires the management of a SerDes DV group focusing on MDV verification including: Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers.The role requires the ability to work with the existing functional...

Location preference : Bangalore. Work experience : 8+ years.Job Description :- Develop verification plan by understanding requirement.- Create constrained random verification ENV/ TB architecture usingSystem verilog & UVM.- Exposed to Power aware simulation & GLS.- Formal verification & Assertion will be added advantage.- Execute coverage plan & code cov...

Location preference : Bangalore. Work experience : 8+ years. Job Description :- Develop verification plan by understanding requirement.- Create constrained random verification ENV/ TB architecture usingSystem verilog & UVM.- Exposed to Power aware simulation & GLS.- Formal verification & Assertion will be added advantage.- Execute coverage plan & code cov...

Greetings from Wipro !!Wipro is currently hiring for enthusiastic Design verification engineers and the details are as below.Years of experience: 5 to 20 years.Area of expertise: system verilog and UVM, OVM, CPU verification, IP and SOC level verification.Positions: lead level Locations: Bangalore, Hyderabad.Job description:. BE/ B.Tech/ Master degree in...

Hi,My name is Vijay, and I am a TA Specalist at LeadSoc Technologies Pvt Ltd., We have multiple projects on Design verification with Multiple Products.About us:LeadSoC Technologies offers cutting-edge Engineering Design services in VLSI and Embedded Systems. We have been growing rapidly over the last 5 years to meet the evolving needs of the Semiconductor,...