Senior FPGA Engineer

3 months ago

Hyderabad, India Synopsys Inc Full time

Senior/Staff Application Engineer (FPGA Emulation/Simulation) – HW Solution:

  • Experience : 4yrs to 12 years
  • Location: Hyderabad
  • Seeking a highly motivated and innovative hardware engineer. Working as part of a highly experienced emulation team, the candidate will be contributing towards improving the quality of Synopsys Emulation (ZEBU) and integration tool.
  • The position offers an excellent opportunity to work with an expert team of emulation engineers & architects responsible for qualifying emulation product and it's solution from specification development to performing functional and performance tests for validating the interoperability methodology for emulation solution.
  • In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, verification protocols including VCS, Verdi, PCIE, Ethernet, USB, CXL as well as Xilinx FPGA Vivado tool. Role would also provide opportunity to verify protocol solutions for customers for complex emulation problems.
  • Requirements:
  • B. Tech/M. Tech in EEE/ECE/ETE/VLSI engineering with 4-10 years hands-on experience in emulation/simulation and verification IPs.
  • Knowledge on areas like Synthesis, Simulation, Verification, place and route with FPGA is preferred.
  • Knowledge and experience on Hardware emulation tool or experience in verification technology, testcase creation, simulation using VCS or other simulators, debugging with Verdi/DVE is must.
  • Must be proficient multi-taskers to ensure all aspects of engineering a product are addressed. Familiarity with scripting languages, verification IP protocols are a plus.
  • Should have good organization and communication skills for interacting with R&D and AEs teams.
  • Responsibilities :
  • The candidate will be responsible for validation of Emulation product (ZeBu) and various solutions for emulation product.
  • The engineer will also design and develop tests in VHDL/Verilog/System Verilog languages, resolving synthesis and place & route with FPGA to validate the tool.
  • Responsible for analyzing customer designs & in-house, modifying block-level test benches, executing verification plans, analysis/debugging RTL, and gate-level emulation failures, performing gate-level emulations, interacting with R&D and AE teams.
  • Candidate will also be responsible for developing validation strategy and coverage driven plan for newer solutions and take it to production working with R&D and AE teams.

Please share your updated CV to or refer who would like to explore this opportunity.

  • Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.

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